57 lines
2.7 KiB
VHDL
57 lines
2.7 KiB
VHDL
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ARCHITECTURE RTL OF instructionDecoder IS
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constant opCodeIndexH : integer := instruction'high;
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constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1;
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constant twoRegInstrIndex : integer := opCodeIndexL - 1;
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constant ioAddrIndexed : integer := twoRegInstrIndex;
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constant addrAIndexH : integer := twoRegInstrIndex - 1;
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constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1;
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constant immediateDataIndexH : integer := registerBitNb-1;
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constant immediateDataIndexL : integer := 0;
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constant addrBIndexH : integer := addrAIndexL - 1;
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constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1;
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constant aluCodeIndexH : integer := opCodeIndexH;
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constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1;
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constant portAddressH : integer := registerBitNb-1;
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constant portAddressL : integer := portAddressH-portAddressBitNb+1;
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constant spadAddressH : integer := registerBitNb-1;
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constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1;
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constant branchCondH : integer := opCodeIndexL-1;
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constant branchCondL : integer := branchCondH-branchCondBitNb+1;
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BEGIN
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------------------------------------------------------------------------------
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-- ALU control
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aluCode <=
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instruction(aluCodeIndexH downto aluCodeIndexL)
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when instruction(aluCodeIndexH) = '0' else
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'1' & instruction(aluCodeBitNb-2 downto 0);
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opCode <= instruction(opCodeIndexH downto opCodeIndexL);
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twoRegInstr <= instruction(twoRegInstrIndex);
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addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL));
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addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL));
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instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL));
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------------------------------------------------------------------------------
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-- I/O control
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portIndexedSel <= instruction(ioAddrIndexed);
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portAddress <= unsigned(instruction(portAddressH downto portAddressL));
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------------------------------------------------------------------------------
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-- scratchpad control
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spadIndexedSel <= instruction(ioAddrIndexed);
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spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL));
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------------------------------------------------------------------------------
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-- branch control
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branchCond <= instruction(branchCondH downto branchCondL);
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instrAddress <= unsigned(instruction(instrAddress'range));
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END ARCHITECTURE RTL;
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