37 lines
1.0 KiB
VHDL
37 lines
1.0 KiB
VHDL
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library ieee;
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use std.textio.all;
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use ieee.std_logic_textio.all;
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ARCHITECTURE hex OF instrMemory IS
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-- Instructions type
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type t_instrBank is array (0 to (2**g_memoryNbBits)-1) of
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std_ulogic_vector(g_dataWidth-1 downto 0);
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-- Define function to create initvalue signal
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impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is
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FILE ramContentFile : text is in ramContentFilenAme;
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variable ramContentFileLine : line;
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variable ramContent : t_instrBank;
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begin
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for i in t_instrBank'range loop
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readline(ramContentFile, ramContentFileLine);
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HREAD(ramContentFileLine, ramContent(i));
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end loop;
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return ramContent;
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end function;
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-- Program
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constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile);
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BEGIN
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-- Comb. read
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process(PC)
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begin
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-- skip the two last bits (since we do only +4)
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instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2))) after g_tMemRd;
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end process;
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END ARCHITECTURE hex;
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