SEm-Labos/Libs/RiscV/HEIRV32/SingleCycle/hds/heirv32_sc/struct.bd

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stg "VerticalLayoutStrategy"
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xt "16600,82700,19700,83700"
st "gates"
blo "16600,83500"
tm "BdLibraryNameMgr"
)
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xt "16600,83700,26300,84700"
st "mux2to1Unsigned"
blo "16600,84500"
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uid 827,0
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xt "16600,84700,21500,85700"
st "U_pcMux"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
matrix (Matrix
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text (MLText
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xt "16000,86000,34500,88000"
st "dataBitNb = c_dataWidth    ( positive )  
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header ""
)
elements [
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type "positive"
value "c_dataWidth"
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viewicon (ZoomableIcon
uid 831,0
sl 0
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xt "20250,81250,21750,82750"
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iconMaskName "VhdlFileViewIcon.msk"
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viewiconposition 0
portVis (PortSigDisplay
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sTC 0
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uid 1362,0
lang 11
decl (Decl
n "zero"
t "std_ulogic"
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declText (MLText
uid 1363,0
va (VaSet
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xt "22000,39200,41000,40000"
st "SIGNAL zero            : std_ulogic"
)
)
*25 (Net
uid 1376,0
lang 11
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 downto 0)"
o 26
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declText (MLText
uid 1377,0
va (VaSet
font "Courier New,8,0"
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xt "22000,36000,51000,36800"
st "SIGNAL resultSrc       : std_ulogic_vector(1 downto 0)"
)
)
*26 (Net
uid 1388,0
lang 11
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 7
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)
declText (MLText
uid 1389,0
va (VaSet
font "Courier New,8,0"
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xt "22000,20800,51000,21600"
st "SIGNAL ALUControl      : std_ulogic_vector(2 DOWNTO 0)"
)
)
*27 (Net
uid 1434,0
lang 11
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 19
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declText (MLText
uid 1435,0
va (VaSet
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xt "22000,30400,51000,31200"
st "SIGNAL immSrc          : std_ulogic_vector(1 DOWNTO 0)"
)
)
*28 (Net
uid 1436,0
lang 11
decl (Decl
n "regwrite"
t "std_ulogic"
o 24
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declText (MLText
uid 1437,0
va (VaSet
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xt "22000,34400,41000,35200"
st "SIGNAL regwrite        : std_ulogic"
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)
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uid 1662,0
lang 11
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
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)
declText (MLText
uid 1663,0
va (VaSet
font "Courier New,8,0"
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xt "22000,31200,57000,32000"
st "SIGNAL instruction     : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)"
)
)
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uid 2122,0
lang 11
decl (Decl
n "immExt"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
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)
declText (MLText
uid 2123,0
va (VaSet
font "Courier New,8,0"
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xt "22000,29600,57000,30400"
st "SIGNAL immExt          : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)"
)
)
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uid 2450,0
lang 11
decl (Decl
n "srcA"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 27
suid 74,0
)
declText (MLText
uid 2451,0
va (VaSet
font "Courier New,8,0"
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xt "22000,36800,57000,37600"
st "SIGNAL srcA            : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)"
)
)
*32 (Net
uid 2452,0
lang 11
decl (Decl
n "srcB"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 28
suid 75,0
)
declText (MLText
uid 2453,0
va (VaSet
font "Courier New,8,0"
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xt "22000,37600,57000,38400"
st "SIGNAL srcB            : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)"
)
)
*33 (Net
uid 2595,0
lang 11
decl (Decl
n "ALUResult"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 8
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)
declText (MLText
uid 2596,0
va (VaSet
font "Courier New,8,0"
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xt "22000,21600,57000,22400"
st "SIGNAL ALUResult       : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)"
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uid 4351,0
lang 11
decl (Decl
n "dbg_leds"
t "std_ulogic_vector"
b "(31 DOWNTO 0)"
o 5
suid 93,0
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declText (MLText
uid 4352,0
va (VaSet
font "Courier New,8,0"
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xt "22000,5600,48000,6400"
st "dbg_leds        : std_ulogic_vector(31 DOWNTO 0)"
)
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uid 4365,0
shape (CompositeShape
uid 4366,0
va (VaSet
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fg "0,0,32768"
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uid 4367,0
sl 0
ro 270
xt "173500,13625,175000,14375"
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(Line
uid 4368,0
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ro 270
xt "173000,14000,173500,14000"
pts [
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)
stc 0
sf 1
tg (WTG
uid 4369,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4370,0
va (VaSet
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xt "176000,13400,181200,14600"
st "dbg_leds"
blo "176000,14400"
tm "WireNameMgr"
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)
)
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va (VaSet
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fg "65535,65535,65535"
lineColor "0,0,32768"
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xt "118000,10000,170000,26000"
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oxt "0,0,18000,5000"
text (MLText
uid 4481,0
va (VaSet
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xt "118200,10200,170000,24600"
st "


dbg_leds(7 downto 0) <= std_ulogic_vector(PC(9 downto 2)); -- no need to read LSBs since does +4 each time

dbg_leds(14 downto 8) <= instruction(6 downto 0); -- op

dbg_leds(17 downto 15) <= instruction(14 downto 12); -- funct3

dbg_leds(18) <= instruction(30); -- funct7

dbg_leds(31 downto 19) <= (others => '0'); -- not used

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tm "HdlTextMgr"
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shape (Rectangle
uid 4374,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
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xt "118000,9000,170000,28000"
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oxt "0,0,8000,10000"
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ps "CenterOffsetStrategy"
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uid 4376,0
va (VaSet
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xt "127800,30000,129000,31200"
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viewicon (ZoomableIcon
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sl 0
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fg "49152,49152,49152"
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xt "118250,26250,119750,27750"
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iconMaskName "TextFile.msk"
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uid 4490,0
shape (CompositeShape
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va (VaSet
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tg (WTG
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f (Text
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va (VaSet
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ju 2
blo "8000,42400"
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uid 4496,0
lang 11
decl (Decl
n "en"
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declText (MLText
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xt "22000,4000,37500,4800"
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uid 5835,0
lang 11
decl (Decl
n "btns"
t "std_ulogic_vector"
b "(g_btnsNb-1 DOWNTO 0)"
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)
declText (MLText
uid 5836,0
va (VaSet
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xt "22000,2400,52000,3200"
st "btns            : std_ulogic_vector(g_btnsNb-1 DOWNTO 0)"
)
)
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uid 5841,0
shape (CompositeShape
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va (VaSet
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uid 5843,0
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sl 0
ro 270
xt "90500,88000,91000,88000"
pts [
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]
)
stc 0
sf 1
tg (WTG
uid 5845,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5846,0
va (VaSet
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xt "85100,87400,88000,88600"
st "btns"
ju 2
blo "88000,88400"
tm "WireNameMgr"
)
)
)
*44 (Net
uid 5847,0
lang 11
decl (Decl
n "leds"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 6
suid 102,0
)
declText (MLText
uid 5848,0
va (VaSet
font "Courier New,8,0"
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xt "22000,6400,53500,7200"
st "leds            : std_ulogic_vector(g_dataWidth-1 DOWNTO 0)"
)
)
*45 (PortIoOut
uid 5853,0
shape (CompositeShape
uid 5854,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 5855,0
sl 0
ro 90
xt "89000,88625,90500,89375"
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(Line
uid 5856,0
sl 0
ro 90
xt "90500,89000,91000,89000"
pts [
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"90500,89000"
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]
)
stc 0
sf 1
tg (WTG
uid 5857,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "85200,88400,88000,89600"
st "leds"
ju 2
blo "88000,89400"
tm "WireNameMgr"
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)
)
*46 (Net
uid 7050,0
lang 11
decl (Decl
n "PCTarget"
t "unsigned"
b "(c_dataWidth - 1 downto 0)"
o 15
suid 103,0
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declText (MLText
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va (VaSet
font "Courier New,8,0"
)
xt "22000,27200,53500,28000"
st "SIGNAL PCTarget        : unsigned(c_dataWidth - 1 downto 0)"
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)
*47 (Net
uid 7052,0
lang 11
decl (Decl
n "PCPlus4"
t "unsigned"
b "(c_dataWidth - 1 downto 0)"
o 12
suid 104,0
)
declText (MLText
uid 7053,0
va (VaSet
font "Courier New,8,0"
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xt "22000,24800,53500,25600"
st "SIGNAL PCPlus4         : unsigned(c_dataWidth - 1 downto 0)"
)
)
*48 (Net
uid 7054,0
decl (Decl
n "PCNext"
t "unsigned"
b "(c_dataWidth-1 DOWNTO 0)"
o 11
suid 105,0
)
declText (MLText
uid 7055,0
va (VaSet
font "Courier New,8,0"
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xt "22000,24000,52500,24800"
st "SIGNAL PCNext          : unsigned(c_dataWidth-1 DOWNTO 0)"
)
)
*49 (Net
uid 7170,0
decl (Decl
n "PCSrc"
t "std_uLogic"
o 14
suid 107,0
)
declText (MLText
uid 7171,0
va (VaSet
font "Courier New,8,0"
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xt "22000,26400,41000,27200"
st "SIGNAL PCSrc           : std_uLogic"
)
)
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uid 7180,0
lang 11
decl (Decl
n "PC"
t "unsigned"
b "(c_dataWidth - 1 DOWNTO 0)"
o 10
suid 109,0
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declText (MLText
uid 7181,0
va (VaSet
font "Courier New,8,0"
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xt "22000,23200,53500,24000"
st "SIGNAL PC              : unsigned(c_dataWidth - 1 DOWNTO 0)"
)
)
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optionalChildren [
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ps "OnEdgeStrategy"
shape (Triangle
uid 7191,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40250,86625,41000,87375"
)
tg (CPTG
uid 7192,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7193,0
va (VaSet
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xt "41000,86400,43300,87600"
st "in1"
blo "41000,87400"
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s (Text
uid 7194,0
va (VaSet
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xt "41000,87600,41000,87600"
blo "41000,87600"
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)
thePort (LogicalPort
decl (Decl
n "in1"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
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)
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uid 7195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7196,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "46000,88625,46750,89375"
)
tg (CPTG
uid 7197,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7198,0
va (VaSet
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xt "43000,88400,46000,89600"
st "out1"
ju 2
blo "46000,89400"
)
s (Text
uid 7199,0
va (VaSet
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xt "46000,89600,46000,89600"
ju 2
blo "46000,89600"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*54 (CptPort
uid 7200,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7201,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "40250,90625,41000,91375"
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tg (CPTG
uid 7202,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "41000,90400,43300,91600"
st "in2"
blo "41000,91400"
)
s (Text
uid 7204,0
va (VaSet
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xt "41000,91600,41000,91600"
blo "41000,91600"
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)
thePort (LogicalPort
decl (Decl
n "in2"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 2003,0
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shape (Alu
uid 7206,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "41000,85000,46000,93000"
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showPorts 0
oxt "35000,16000,40000,24000"
ttg (MlTextGroup
uid 7207,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 7208,0
va (VaSet
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xt "34910,91700,38910,92700"
st "operators"
blo "34910,92500"
tm "BdLibraryNameMgr"
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*56 (Text
uid 7209,0
va (VaSet
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xt "34910,92700,40710,93700"
st "addUnsigned"
blo "34910,93500"
tm "CptNameMgr"
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uid 7210,0
va (VaSet
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xt "34910,93700,39610,94700"
st "U_PCAdder"
blo "34910,94500"
tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
matrix (Matrix
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text (MLText
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va (VaSet
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font "Courier New,8,0"
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xt "41000,95800,63500,97400"
st "dataBitNb = c_dataWidth    ( positive )  
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)
header ""
)
elements [
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type "positive"
value "c_dataWidth"
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viewicon (ZoomableIcon
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sl 0
va (VaSet
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xt "41250,91250,42750,92750"
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iconMaskName "VhdlFileViewIcon.msk"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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tg (CPTG
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va (VaSet
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xt "126000,91400,128300,92600"
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s (Text
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va (VaSet
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xt "126000,92600,126000,92600"
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o 1
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ps "OnEdgeStrategy"
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ro 90
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xt "131000,93625,131750,94375"
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tg (CPTG
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va (VaSet
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xt "128000,93400,131000,94600"
st "out1"
ju 2
blo "131000,94400"
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s (Text
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va (VaSet
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xt "131000,94600,131000,94600"
ju 2
blo "131000,94600"
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thePort (LogicalPort
m 1
decl (Decl
n "out1"
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ro 90
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xt "125250,95625,126000,96375"
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tg (CPTG
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va (VaSet
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xt "126000,95400,128300,96600"
st "in2"
blo "126000,96400"
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s (Text
uid 7323,0
va (VaSet
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xt "126000,96600,126000,96600"
blo "126000,96600"
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)
thePort (LogicalPort
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shape (Alu
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va (VaSet
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fg "0,65535,0"
lineColor "0,32896,0"
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xt "126000,90000,131000,98000"
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oxt "35000,16000,40000,24000"
ttg (MlTextGroup
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 7302,0
va (VaSet
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xt "126910,97700,130910,98700"
st "operators"
blo "126910,98500"
tm "BdLibraryNameMgr"
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lang 11
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o 11
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m 1
decl (Decl
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layer 8
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layer 8
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xt "83000,88600,106500,92600"
st "g_dataWidth = c_dataWidth    ( positive )  
g_btnsNb    = g_btnsNb       ( positive )  
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header ""
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m 1
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st "immSrc"
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m 1
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ro 90
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xt "98000,46625,98750,47375"
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st "memWrite"
ju 2
blo "97000,47300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "memWrite"
t "std_ulogic"
o 9
suid 8,0
)
)
)
*230 (CptPort
uid 9772,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9773,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "81250,51625,82000,52375"
)
tg (CPTG
uid 9774,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9775,0
va (VaSet
font "Verdana,8,0"
)
xt "83000,51500,84500,52500"
st "op"
blo "83000,52300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 3
suid 9,0
)
)
)
*231 (CptPort
uid 9776,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9777,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "81250,44625,82000,45375"
)
tg (CPTG
uid 9778,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9779,0
va (VaSet
font "Verdana,8,0"
)
xt "83000,44500,85800,45500"
st "PCSrc"
blo "83000,45300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "PCSrc"
t "std_uLogic"
o 7
suid 10,0
)
)
)
*232 (CptPort
uid 9780,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9781,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91625,59000,92375,59750"
)
tg (CPTG
uid 9782,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9783,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "91500,54200,92500,58000"
st "regwrite"
blo "92300,58000"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "regwrite"
t "std_ulogic"
o 10
suid 11,0
)
)
)
*233 (CptPort
uid 9784,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9785,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,44625,98750,45375"
)
tg (CPTG
uid 9786,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9787,0
va (VaSet
font "Verdana,8,0"
)
xt "93100,44500,97000,45500"
st "resultSrc"
ju 2
blo "97000,45300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 downto 0)"
o 11
suid 12,0
)
)
)
*234 (CptPort
uid 9788,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9789,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98000,56625,98750,57375"
)
tg (CPTG
uid 9790,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9791,0
va (VaSet
font "Verdana,8,0"
)
xt "94800,56500,97000,57500"
st "zero"
ju 2
blo "97000,57300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "zero"
t "std_ulogic"
o 4
suid 14,0
)
)
)
]
shape (Rectangle
uid 9793,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "82000,44000,98000,59000"
)
oxt "16000,23000,32000,38000"
ttg (MlTextGroup
uid 9794,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*235 (Text
uid 9795,0
va (VaSet
font "Verdana,9,1"
)
xt "81800,59800,89200,61000"
st "HEIRV32_SC"
blo "81800,60800"
tm "BdLibraryNameMgr"
)
*236 (Text
uid 9796,0
va (VaSet
font "Verdana,9,1"
)
xt "81800,61000,88600,62200"
st "controlUnit"
blo "81800,62000"
tm "CptNameMgr"
)
*237 (Text
uid 9797,0
va (VaSet
font "Verdana,9,1"
)
xt "81800,62200,89900,63400"
st "U_controlUnit"
blo "81800,63200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9798,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9799,0
text (MLText
uid 9800,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "82000,63200,98000,64000"
st "g_tDec = c_tDec    ( time )  "
)
header ""
)
elements [
(GiElement
name "g_tDec"
type "time"
value "c_tDec"
)
]
)
viewicon (ZoomableIcon
uid 9801,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "82250,57250,83750,58750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*238 (SaComponent
uid 9810,0
optionalChildren [
*239 (CptPort
uid 9802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9803,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "60000,81625,60750,82375"
)
tg (CPTG
uid 9804,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9805,0
va (VaSet
font "Verdana,12,0"
)
xt "50800,81300,59000,82700"
st "instruction"
ju 2
blo "59000,82500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 26
suid 3,0
)
)
)
*240 (CptPort
uid 9806,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,79625,52000,80375"
)
tg (CPTG
uid 9808,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9809,0
va (VaSet
font "Verdana,12,0"
)
xt "53000,79300,55500,80700"
st "PC"
blo "53000,80500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "PC"
t "unsigned"
b "(g_dataWidth - 1 DOWNTO 0)"
o 32
suid 4,0
)
)
)
]
shape (Rectangle
uid 9811,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "52000,78000,60000,85000"
)
oxt "18000,18000,26000,25000"
ttg (MlTextGroup
uid 9812,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*241 (Text
uid 9813,0
va (VaSet
font "Verdana,9,1"
)
xt "52300,85800,59700,87000"
st "HEIRV32_SC"
blo "52300,86800"
tm "BdLibraryNameMgr"
)
*242 (Text
uid 9814,0
va (VaSet
font "Verdana,9,1"
)
xt "52300,87000,59700,88200"
st "instrMemory"
blo "52300,88000"
tm "CptNameMgr"
)
*243 (Text
uid 9815,0
va (VaSet
font "Verdana,9,1"
)
xt "52300,88200,61000,89400"
st "U_instrMemory"
blo "52300,89200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9816,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9817,0
text (MLText
uid 9818,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "52000,89600,78500,92800"
st "g_dataWidth    = c_dataWidth       ( positive )  
g_memoryNbBits = g_memoryNbBits    ( positive )  
g_programFile  = g_programFile     ( string   )  
g_tMemRd       = c_tMemRd          ( time     )  "
)
header ""
)
elements [
(GiElement
name "g_dataWidth"
type "positive"
value "c_dataWidth"
)
(GiElement
name "g_memoryNbBits"
type "positive"
value "g_memoryNbBits"
)
(GiElement
name "g_programFile"
type "string"
value "g_programFile"
)
(GiElement
name "g_tMemRd"
type "time"
value "c_tMemRd"
)
]
)
viewicon (ZoomableIcon
uid 9819,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "52250,83250,53750,84750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*244 (SaComponent
uid 9909,0
optionalChildren [
*245 (CptPort
uid 9877,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9878,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,79625,157000,80375"
)
tg (CPTG
uid 9879,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9880,0
va (VaSet
font "Verdana,8,0"
)
xt "158000,79500,161600,80500"
st "address"
blo "158000,80300"
)
)
thePort (LogicalPort
decl (Decl
n "address"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 30
suid 1,0
)
)
)
*246 (CptPort
uid 9881,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9882,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "158625,72250,159375,73000"
)
tg (CPTG
uid 9883,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9884,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "158453,73307,159453,74907"
st "clk"
ju 2
blo "159253,73307"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*247 (CptPort
uid 9885,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9886,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "163625,72250,164375,73000"
)
tg (CPTG
uid 9887,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9888,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "163500,74000,164500,75500"
st "en"
ju 2
blo "164300,74000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*248 (CptPort
uid 9889,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9890,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,76625,157000,77375"
)
tg (CPTG
uid 9891,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9892,0
va (VaSet
font "Verdana,8,0"
)
xt "158000,76500,161500,77500"
st "writeEn"
blo "158000,77300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeEn"
t "std_ulogic"
o 29
suid 4,0
)
)
)
*249 (CptPort
uid 9893,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9894,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "166000,82625,166750,83375"
)
tg (CPTG
uid 9895,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9896,0
va (VaSet
font "Verdana,8,0"
)
xt "160800,82500,165000,83500"
st "readData"
ju 2
blo "165000,83300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "readData"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 32
suid 5,0
)
)
)
*250 (CptPort
uid 9897,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9898,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160625,72250,161375,73000"
)
tg (CPTG
uid 9899,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9900,0
ro 270
va (VaSet
font "Verdana,8,0"
)
xt "160500,74000,161500,75500"
st "rst"
ju 2
blo "161300,74000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 4
suid 6,0
)
)
)
*251 (CptPort
uid 9901,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9902,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "156250,87625,157000,88375"
)
tg (CPTG
uid 9903,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9904,0
va (VaSet
font "Verdana,8,0"
)
xt "158000,87500,162400,88500"
st "writeData"
blo "158000,88300"
)
)
thePort (LogicalPort
decl (Decl
n "writeData"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 31
suid 7,0
)
)
)
*252 (CommentGraphic
uid 9905,0
shape (PolyLine2D
pts [
"158000,73000"
"159000,75000"
]
uid 9906,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "158000,73000,159000,75000"
)
oxt "18000,14000,19000,16000"
)
*253 (CommentGraphic
uid 9907,0
shape (PolyLine2D
pts [
"160000,73000"
"159000,75000"
]
uid 9908,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "159000,73000,160000,75000"
)
oxt "19000,14000,20000,16000"
)
]
shape (Rectangle
uid 9910,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "157000,73000,166000,91000"
fos 1
)
oxt "17000,14000,26000,32000"
ttg (MlTextGroup
uid 9911,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*254 (Text
uid 9912,0
va (VaSet
font "Verdana,9,1"
)
xt "157300,91800,164700,93000"
st "HEIRV32_SC"
blo "157300,92800"
tm "BdLibraryNameMgr"
)
*255 (Text
uid 9913,0
va (VaSet
font "Verdana,9,1"
)
xt "157300,93000,164700,94200"
st "dataMemory"
blo "157300,94000"
tm "CptNameMgr"
)
*256 (Text
uid 9914,0
va (VaSet
font "Verdana,9,1"
)
xt "157300,94200,166000,95400"
st "U_dataMemory"
blo "157300,95200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9915,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9916,0
text (MLText
uid 9917,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "157000,95600,183500,99600"
st "g_dataWidth    = c_dataWidth       ( positive )  
g_memoryNbBits = g_memoryNbBits    ( positive )  
g_tMemWr       = c_tMemWr          ( time     )  
g_tMemRd       = c_tMemRd          ( time     )  
g_tSetup       = c_tSetup          ( time     )  "
)
header ""
)
elements [
(GiElement
name "g_dataWidth"
type "positive"
value "c_dataWidth"
)
(GiElement
name "g_memoryNbBits"
type "positive"
value "g_memoryNbBits"
)
(GiElement
name "g_tMemWr"
type "time"
value "c_tMemWr"
)
(GiElement
name "g_tMemRd"
type "time"
value "c_tMemRd"
)
(GiElement
name "g_tSetup"
type "time"
value "c_tSetup"
)
]
)
viewicon (ZoomableIcon
uid 9918,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "157250,89250,158750,90750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
sed 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*257 (Wire
uid 342,0
shape (OrthoPolyLine
uid 343,0
va (VaSet
vasetType 3
)
xt "11000,38000,14000,38000"
pts [
"11000,38000"
"14000,38000"
]
)
start &12
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 349,0
va (VaSet
isHidden 1
)
xt "13000,36800,15200,38000"
st "clk"
blo "13000,37800"
tm "WireNameMgr"
)
)
on &15
)
*258 (Wire
uid 350,0
shape (OrthoPolyLine
uid 351,0
va (VaSet
vasetType 3
)
xt "11000,40000,14000,40000"
pts [
"11000,40000"
"14000,40000"
]
)
start &13
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 356,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 357,0
va (VaSet
isHidden 1
)
xt "13000,38800,15100,40000"
st "rst"
blo "13000,39800"
tm "WireNameMgr"
)
)
on &14
)
*259 (Wire
uid 782,0
optionalChildren [
*260 (BdJunction
uid 8907,0
ps "OnConnectorStrategy"
shape (Circle
uid 8908,0
va (VaSet
vasetType 1
)
xt "47600,96600,48400,97400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 783,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "12000,79000,48000,97000"
pts [
"46000,89000"
"48000,89000"
"48000,97000"
"12000,97000"
"12000,79000"
"20000,79000"
]
)
start &53
end &17
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 786,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 787,0
va (VaSet
)
xt "15000,77800,20100,79000"
st "PCPlus4"
blo "15000,78800"
tm "WireNameMgr"
)
)
on &47
)
*261 (Wire
uid 852,0
shape (OrthoPolyLine
uid 853,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "24000,80000,29250,80000"
pts [
"24000,80000"
"29250,80000"
]
)
start &18
end &178
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 856,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 857,0
va (VaSet
)
xt "25000,78800,29600,80000"
st "PCNext"
blo "25000,79800"
tm "WireNameMgr"
)
s (Text
uid 2895,0
va (VaSet
)
xt "25000,80000,25000,80000"
blo "25000,80000"
tm "SignalTypeMgr"
)
)
on &48
)
*262 (Wire
uid 1322,0
shape (OrthoPolyLine
uid 1323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,51960,81250,52000"
pts [
"68000,51960"
"74000,51960"
"74000,52000"
"81250,52000"
]
)
start *263 (Ripper
uid 7269,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,50960"
"68000,51960"
]
uid 7270,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,50960,68000,51960"
)
)
end &230
sat 32
eat 32
sty 1
sl "(6 DOWNTO 0)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1327,0
va (VaSet
)
xt "70000,50800,79400,52000"
st "instruction(6:0)"
blo "70000,51800"
tm "WireNameMgr"
)
)
on &29
)
*264 (Wire
uid 1333,0
shape (OrthoPolyLine
uid 1334,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,54000,81250,54000"
pts [
"68000,54000"
"81250,54000"
]
)
start *265 (Ripper
uid 7271,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,53000"
"68000,54000"
]
uid 7272,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,53000,68000,54000"
)
)
end &226
sat 32
eat 32
sty 1
sl "(14 DOWNTO 12)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1337,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1338,0
va (VaSet
)
xt "70000,52800,80800,54000"
st "instruction(14:12)"
blo "70000,53800"
tm "WireNameMgr"
)
)
on &29
)
*266 (Wire
uid 1344,0
shape (OrthoPolyLine
uid 1345,0
va (VaSet
vasetType 3
)
xt "68000,56000,81250,56000"
pts [
"68000,56000"
"81250,56000"
]
)
start *267 (Ripper
uid 7273,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,55000"
"68000,56000"
]
uid 7274,0
va (VaSet
vasetType 3
)
xt "67000,55000,68000,56000"
)
)
end &227
sat 32
eat 32
sl "(30)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1349,0
va (VaSet
)
xt "70000,54800,79000,56000"
st "instruction(30)"
blo "70000,55800"
tm "WireNameMgr"
)
)
on &29
)
*268 (Wire
uid 1354,0
shape (OrthoPolyLine
uid 1355,0
va (VaSet
vasetType 3
)
xt "98750,57000,138000,78000"
pts [
"135750,78000"
"138000,78000"
"138000,57000"
"98750,57000"
]
)
start &201
end &234
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1360,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1361,0
va (VaSet
)
xt "101000,55800,103800,57000"
st "zero"
blo "101000,56800"
tm "WireNameMgr"
)
)
on &24
)
*269 (Wire
uid 1380,0
shape (OrthoPolyLine
uid 1381,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,49000,131000,73027"
pts [
"98750,49000"
"131000,49000"
"131000,73027"
]
)
start &224
end &197
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1386,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1387,0
va (VaSet
)
xt "101000,47800,108300,49000"
st "ALUControl"
blo "101000,48800"
tm "WireNameMgr"
)
)
on &26
)
*270 (Wire
uid 1412,0
shape (OrthoPolyLine
uid 1413,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,53000,105000,94000"
pts [
"98750,53000"
"105000,53000"
"105000,94000"
"99750,94000"
]
)
start &228
end &169
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1419,0
va (VaSet
)
xt "100750,51800,105250,53000"
st "immSrc"
blo "100750,52800"
tm "WireNameMgr"
)
)
on &27
)
*271 (Wire
uid 1794,0
optionalChildren [
*272 (Ripper
uid 1832,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,96000"
"68000,97000"
]
uid 1833,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,96000,68000,97000"
)
)
&263
&265
&267
*273 (BdJunction
uid 7281,0
ps "OnConnectorStrategy"
shape (Circle
uid 7282,0
va (VaSet
vasetType 1
)
xt "66600,81600,67400,82400"
radius 400
)
)
*274 (Ripper
uid 7293,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,74000"
"68000,75000"
]
uid 7294,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,74000,68000,75000"
)
)
*275 (Ripper
uid 7295,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,76000"
"68000,77000"
]
uid 7296,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,76000,68000,77000"
)
)
*276 (Ripper
uid 7297,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"67000,78000"
"68000,79000"
]
uid 7298,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,78000,68000,79000"
)
)
]
shape (OrthoPolyLine
uid 1795,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,49000,67000,98000"
pts [
"67000,49000"
"67000,98000"
]
)
sat 16
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1798,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1799,0
ro 270
va (VaSet
isHidden 1
)
xt "65800,47000,67000,53800"
st "instruction"
blo "66800,53800"
tm "WireNameMgr"
)
)
on &29
)
*277 (Wire
uid 1802,0
shape (OrthoPolyLine
uid 1803,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,75000,81250,75000"
pts [
"68000,75000"
"81250,75000"
]
)
start &274
end &207
sat 32
eat 32
sty 1
sl "(19 DOWNTO 15)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1806,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1807,0
va (VaSet
)
xt "71000,73800,81800,75000"
st "instruction(19:15)"
blo "71000,74800"
tm "WireNameMgr"
)
)
on &29
)
*278 (Wire
uid 1810,0
shape (OrthoPolyLine
uid 1811,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,77000,81250,77000"
pts [
"68000,77000"
"81250,77000"
]
)
start &275
end &213
sat 32
eat 32
sty 1
sl "(24 DOWNTO 20)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1814,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1815,0
va (VaSet
)
xt "71000,75800,81800,77000"
st "instruction(24:20)"
blo "71000,76800"
tm "WireNameMgr"
)
)
on &29
)
*279 (Wire
uid 1818,0
shape (OrthoPolyLine
uid 1819,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,79000,81250,79000"
pts [
"68000,79000"
"81250,79000"
]
)
start &276
end &214
sat 32
eat 32
sty 1
sl "(11 DOWNTO 7)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1822,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1823,0
va (VaSet
)
xt "71000,77800,81100,79000"
st "instruction(11:7)"
blo "71000,78800"
tm "WireNameMgr"
)
)
on &29
)
*280 (Wire
uid 1826,0
shape (OrthoPolyLine
uid 1827,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "68000,97000,83250,97000"
pts [
"68000,97000"
"83250,97000"
]
)
start &272
end &168
sat 32
eat 32
sty 1
sl "(31 DOWNTO 7)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1830,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1831,0
va (VaSet
)
xt "69000,95800,79100,97000"
st "instruction(31:7)"
blo "69000,96800"
tm "WireNameMgr"
)
)
on &29
)
*281 (Wire
uid 1836,0
shape (OrthoPolyLine
uid 1837,0
va (VaSet
vasetType 3
)
xt "85000,69000,85000,70250"
pts [
"85000,69000"
"85000,70250"
]
)
end &206
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1842,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1843,0
va (VaSet
)
xt "84059,67035,86259,68235"
st "clk"
blo "84059,68035"
tm "WireNameMgr"
)
)
on &15
)
*282 (Wire
uid 1844,0
shape (OrthoPolyLine
uid 1845,0
va (VaSet
vasetType 3
)
xt "88000,69000,88000,70250"
pts [
"88000,69000"
"88000,70250"
]
)
end &212
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1850,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1851,0
va (VaSet
)
xt "87000,67041,89100,68241"
st "rst"
blo "87000,68041"
tm "WireNameMgr"
)
)
on &14
)
*283 (Wire
uid 2096,0
shape (OrthoPolyLine
uid 2097,0
va (VaSet
vasetType 3
)
xt "92000,59750,92000,70250"
pts [
"92000,59750"
"92000,70250"
]
)
start &232
end &211
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2098,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2099,0
va (VaSet
)
xt "92000,60800,96700,62000"
st "regwrite"
blo "92000,61800"
tm "WireNameMgr"
)
)
on &28
)
*284 (Wire
uid 2114,0
optionalChildren [
*285 (BdJunction
uid 7330,0
ps "OnConnectorStrategy"
shape (Circle
uid 7331,0
va (VaSet
vasetType 1
)
xt "108600,96600,109400,97400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 2115,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "99750,97000,116000,97000"
pts [
"99750,97000"
"116000,97000"
]
)
start &167
end &75
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2121,0
va (VaSet
)
xt "111000,95800,115500,97000"
st "immExt"
blo "111000,96800"
tm "WireNameMgr"
)
)
on &30
)
*286 (Wire
uid 2436,0
shape (OrthoPolyLine
uid 2437,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "99750,74000,125250,76000"
pts [
"99750,76000"
"108000,76000"
"108000,74000"
"125250,74000"
]
)
start &209
end &199
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2440,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2441,0
va (VaSet
)
xt "122000,72800,125100,74000"
st "srcA"
blo "122000,73800"
tm "WireNameMgr"
)
s (Text
uid 2925,0
va (VaSet
)
xt "122000,74000,122000,74000"
blo "122000,74000"
tm "SignalTypeMgr"
)
)
on &31
)
*287 (Wire
uid 2444,0
shape (OrthoPolyLine
uid 2445,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "118000,81000,125250,83000"
pts [
"118000,81000"
"122000,81000"
"122000,83000"
"125250,83000"
]
)
start &67
end &200
ss 0
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2448,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2449,0
va (VaSet
)
xt "122255,81800,125255,83000"
st "srcB"
blo "122255,82800"
tm "WireNameMgr"
)
s (Text
uid 2926,0
va (VaSet
)
xt "122255,83000,122255,83000"
blo "122255,83000"
tm "SignalTypeMgr"
)
)
on &32
)
*288 (Wire
uid 2849,0
shape (OrthoPolyLine
uid 2850,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "14000,81000,135000,107000"
pts [
"20000,81000"
"14000,81000"
"14000,107000"
"135000,107000"
"135000,94000"
"131000,94000"
]
)
start &20
end &60
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 2851,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2852,0
va (VaSet
)
xt "15000,79800,20500,81000"
st "PCTarget"
blo "15000,80800"
tm "WireNameMgr"
)
s (Text
uid 2934,0
va (VaSet
)
xt "15000,81000,15000,81000"
blo "15000,81000"
tm "SignalTypeMgr"
)
)
on &46
)
*289 (Wire
uid 3748,0
optionalChildren [
*290 (BdJunction
uid 7584,0
ps "OnConnectorStrategy"
shape (Circle
uid 7585,0
va (VaSet
vasetType 1
)
xt "146600,79600,147400,80400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 3749,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "135750,80000,156250,80000"
pts [
"156250,80000"
"135750,80000"
]
)
start &245
end &198
ss 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3751,0
va (VaSet
)
xt "140000,78800,146100,80000"
st "ALUResult"
blo "140000,79800"
tm "WireNameMgr"
)
)
on &33
)
*291 (Wire
uid 4353,0
shape (OrthoPolyLine
uid 4354,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "170000,14000,173000,14000"
pts [
"173000,14000"
"170000,14000"
]
)
start &35
end &36
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4357,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4358,0
va (VaSet
isHidden 1
)
xt "175000,12800,180200,14000"
st "dbg_leds"
blo "175000,13800"
tm "WireNameMgr"
)
)
on &34
)
*292 (Wire
uid 4484,0
shape (OrthoPolyLine
uid 4485,0
va (VaSet
vasetType 3
)
xt "11000,42000,14000,42000"
pts [
"11000,42000"
"13000,42000"
"14000,42000"
]
)
start &40
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4488,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4489,0
va (VaSet
isHidden 1
)
xt "11000,39800,12900,41000"
st "en"
blo "11000,40800"
tm "WireNameMgr"
)
)
on &41
)
*293 (Wire
uid 4728,0
shape (OrthoPolyLine
uid 4729,0
va (VaSet
vasetType 3
)
xt "95000,69000,95000,70250"
pts [
"95000,69000"
"95000,70250"
]
)
end &215
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4735,0
va (VaSet
)
xt "94155,66800,96055,68000"
st "en"
blo "94155,67800"
tm "WireNameMgr"
)
)
on &41
)
*294 (Wire
uid 5837,0
shape (OrthoPolyLine
uid 5838,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91000,85750,94000,88000"
pts [
"94000,85750"
"94000,88000"
"91000,88000"
]
)
start &216
end &43
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5839,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5840,0
ro 270
va (VaSet
isHidden 1
)
xt "92800,88750,94000,91650"
st "btns"
blo "93800,91650"
tm "WireNameMgr"
)
)
on &42
)
*295 (Wire
uid 5849,0
shape (OrthoPolyLine
uid 5850,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91000,85750,96000,89000"
pts [
"96000,85750"
"96000,89000"
"91000,89000"
]
)
start &217
end &45
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5851,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5852,0
ro 270
va (VaSet
isHidden 1
)
xt "94800,87750,96000,90550"
st "leds"
blo "95800,90550"
tm "WireNameMgr"
)
)
on &44
)
*296 (Wire
uid 7104,0
shape (OrthoPolyLine
uid 7105,0
va (VaSet
vasetType 3
)
xt "26000,82000,29250,82000"
pts [
"26000,82000"
"29250,82000"
]
)
end &180
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 7108,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7109,0
va (VaSet
)
xt "27000,80800,29100,82000"
st "rst"
blo "27000,81800"
tm "WireNameMgr"
)
)
on &14
)
*297 (Wire
uid 7116,0
shape (OrthoPolyLine
uid 7117,0
va (VaSet
vasetType 3
)
xt "32000,75000,32000,76250"
pts [
"32000,75000"
"32000,76250"
]
)
end &176
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 7120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7121,0
va (VaSet
)
xt "31059,73035,33259,74235"
st "clk"
blo "31059,74035"
tm "WireNameMgr"
)
)
on &15
)
*298 (Wire
uid 7122,0
shape (OrthoPolyLine
uid 7123,0
va (VaSet
vasetType 3
)
xt "32000,84750,32000,86000"
pts [
"32000,86000"
"32000,84750"
]
)
end &179
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7126,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7127,0
va (VaSet
)
xt "30000,84800,31900,86000"
st "en"
blo "30000,85800"
tm "WireNameMgr"
)
)
on &41
)
*299 (Wire
uid 7164,0
shape (OrthoPolyLine
uid 7165,0
va (VaSet
vasetType 3
)
xt "23000,45000,81250,78500"
pts [
"23000,78500"
"23000,45000"
"81250,45000"
]
)
start &19
end &231
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 7168,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7169,0
ro 270
va (VaSet
)
xt "21800,73800,23000,77700"
st "PCSrc"
blo "22800,77700"
tm "WireNameMgr"
)
s (Text
uid 7923,0
ro 270
va (VaSet
)
xt "23000,77700,23000,77700"
blo "23000,77700"
tm "SignalTypeMgr"
)
)
on &49
)
*300 (Wire
uid 7174,0
optionalChildren [
*301 (BdJunction
uid 7188,0
ps "OnConnectorStrategy"
shape (Circle
uid 7189,0
va (VaSet
vasetType 1
)
xt "36600,79600,37400,80400"
radius 400
)
)
*302 (BdJunction
uid 7336,0
ps "OnConnectorStrategy"
shape (Circle
uid 7337,0
va (VaSet
vasetType 1
)
xt "48600,79600,49400,80400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 7175,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34750,80000,51250,80000"
pts [
"34750,80000"
"51250,80000"
]
)
start &177
end &240
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7178,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7179,0
va (VaSet
)
xt "35000,78800,37200,80000"
st "PC"
blo "35000,79800"
tm "WireNameMgr"
)
)
on &50
)
*303 (Wire
uid 7182,0
shape (OrthoPolyLine
uid 7183,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "37000,80000,41000,87000"
pts [
"37000,80000"
"37000,87000"
"41000,87000"
]
)
start &301
end &52
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7186,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7187,0
va (VaSet
)
xt "39000,85800,41200,87000"
st "PC"
blo "39000,86800"
tm "WireNameMgr"
)
)
on &50
)
*304 (Wire
uid 7275,0
shape (OrthoPolyLine
uid 7276,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60750,82000,67000,82000"
pts [
"67000,82000"
"60750,82000"
]
)
start &273
end &239
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7279,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7280,0
va (VaSet
)
xt "61000,80800,67800,82000"
st "instruction"
blo "61000,81800"
tm "WireNameMgr"
)
)
on &29
)
*305 (Wire
uid 7324,0
shape (OrthoPolyLine
uid 7325,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "109000,82000,114000,97000"
pts [
"109000,97000"
"109000,82000"
"114000,82000"
]
)
start &285
end &69
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7328,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7329,0
va (VaSet
)
xt "110000,80800,114500,82000"
st "immExt"
blo "110000,81800"
tm "WireNameMgr"
)
)
on &30
)
*306 (Wire
uid 7332,0
shape (OrthoPolyLine
uid 7333,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49000,80000,126000,92000"
pts [
"49000,80000"
"49000,91000"
"122000,91000"
"122000,92000"
"126000,92000"
]
)
start &302
end &59
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7334,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7335,0
va (VaSet
)
xt "123000,90800,125200,92000"
st "PC"
blo "123000,91800"
tm "WireNameMgr"
)
)
on &50
)
*307 (Wire
uid 7370,0
optionalChildren [
*308 (BdJunction
uid 7382,0
ps "OnConnectorStrategy"
shape (Circle
uid 7383,0
va (VaSet
vasetType 1
)
xt "106600,79600,107400,80400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 7371,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "99750,80000,114000,80000"
pts [
"99750,80000"
"114000,80000"
]
)
start &210
end &66
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7373,0
va (VaSet
)
xt "109000,78800,114500,80000"
st "writeData"
blo "109000,79800"
tm "WireNameMgr"
)
)
on &73
)
*309 (Wire
uid 7376,0
shape (OrthoPolyLine
uid 7377,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107000,80000,156250,88000"
pts [
"107000,80000"
"107000,88000"
"156250,88000"
]
)
start &308
end &251
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7381,0
va (VaSet
)
xt "140000,86800,145500,88000"
st "writeData"
blo "140000,87800"
tm "WireNameMgr"
)
)
on &73
)
*310 (Wire
uid 7406,0
shape (OrthoPolyLine
uid 7407,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "121000,96000,126000,97000"
pts [
"121000,97000"
"122000,97000"
"122000,96000"
"126000,96000"
]
)
start &76
end &61
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 7408,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7409,0
va (VaSet
isHidden 1
)
xt "125000,94800,128000,96000"
st "out1"
blo "125000,95800"
tm "WireNameMgr"
)
s (Text
uid 7927,0
va (VaSet
isHidden 1
)
xt "125000,96000,125000,96000"
blo "125000,96000"
tm "SignalTypeMgr"
)
)
on &80
)
*311 (Wire
uid 7424,0
shape (OrthoPolyLine
uid 7425,0
va (VaSet
vasetType 3
)
xt "98750,51000,117000,79500"
pts [
"117000,79500"
"117000,51000"
"98750,51000"
]
)
start &68
end &225
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 7428,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7429,0
va (VaSet
)
xt "101000,49800,105600,51000"
st "ALUSrc"
blo "101000,50800"
tm "WireNameMgr"
)
s (Text
uid 7930,0
va (VaSet
)
xt "101000,51000,101000,51000"
blo "103900,52700"
tm "SignalTypeMgr"
)
)
on &81
)
*312 (Wire
uid 7432,0
shape (OrthoPolyLine
uid 7433,0
va (VaSet
vasetType 3
)
xt "159000,71000,159000,72250"
pts [
"159000,71000"
"159000,72250"
]
)
end &246
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 7438,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7439,0
va (VaSet
)
xt "158059,69035,160259,70235"
st "clk"
blo "158059,70035"
tm "WireNameMgr"
)
)
on &15
)
*313 (Wire
uid 7440,0
shape (OrthoPolyLine
uid 7441,0
va (VaSet
vasetType 3
)
xt "161000,71000,161000,72250"
pts [
"161000,71000"
"161000,72250"
]
)
end &250
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 7446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7447,0
va (VaSet
)
xt "160000,69041,162100,70241"
st "rst"
blo "160000,70041"
tm "WireNameMgr"
)
)
on &14
)
*314 (Wire
uid 7448,0
shape (OrthoPolyLine
uid 7449,0
va (VaSet
vasetType 3
)
xt "164000,71000,164000,72250"
pts [
"164000,71000"
"164000,72250"
]
)
end &247
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7455,0
va (VaSet
)
xt "163155,68800,165055,70000"
st "en"
blo "163155,69800"
tm "WireNameMgr"
)
)
on &41
)
*315 (Wire
uid 7468,0
shape (OrthoPolyLine
uid 7469,0
va (VaSet
vasetType 3
)
xt "98750,47000,156250,77000"
pts [
"98750,47000"
"150000,47000"
"150000,77000"
"156250,77000"
]
)
start &229
end &248
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 7474,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7475,0
va (VaSet
)
xt "101000,45800,106700,47000"
st "memWrite"
blo "101000,46800"
tm "WireNameMgr"
)
)
on &82
)
*316 (Wire
uid 7580,0
shape (OrthoPolyLine
uid 7581,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,63000,177250,81000"
pts [
"147000,80000"
"147000,63000"
"173000,63000"
"173000,81000"
"177250,81000"
]
)
start &290
end &190
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7582,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7583,0
va (VaSet
isHidden 1
)
xt "173000,79800,179100,81000"
st "ALUResult"
blo "173000,80800"
tm "WireNameMgr"
)
)
on &33
)
*317 (Wire
uid 7628,0
shape (OrthoPolyLine
uid 7629,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "77000,83000,189000,103000"
pts [
"81250,83000"
"77000,83000"
"77000,103000"
"189000,103000"
"189000,84000"
"182750,84000"
]
)
start &208
end &192
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7630,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7631,0
va (VaSet
)
xt "184000,82800,187600,84000"
st "result"
blo "184000,83800"
tm "WireNameMgr"
)
)
on &83
)
*318 (Wire
uid 8697,0
shape (OrthoPolyLine
uid 8698,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "31000,91000,41000,91000"
pts [
"41000,91000"
"31000,91000"
]
)
start &54
sat 32
eat 16
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 8701,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8702,0
va (VaSet
)
xt "32000,89800,41200,91000"
st "c_fourUnsigned"
blo "32000,90800"
tm "WireNameMgr"
)
s (Text
uid 8976,0
va (VaSet
)
xt "32000,91000,32000,91000"
blo "32000,91000"
tm "SignalTypeMgr"
)
)
on &84
)
*319 (Wire
uid 8715,0
shape (OrthoPolyLine
uid 8716,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "98750,45000,181000,80749"
pts [
"98750,45000"
"181000,45000"
"181000,80749"
]
)
start &233
end &187
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 8717,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8718,0
va (VaSet
)
xt "101000,43800,106300,45000"
st "resultSrc"
blo "101000,44800"
tm "WireNameMgr"
)
)
on &25
)
*320 (Wire
uid 8815,0
shape (OrthoPolyLine
uid 8816,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "169000,87000,177250,87000"
pts [
"177250,87000"
"169000,87000"
]
)
start &188
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 8819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8820,0
va (VaSet
)
xt "170000,85800,179000,87000"
st "c_zeroUlogVec"
blo "170000,86800"
tm "WireNameMgr"
)
)
on &85
)
*321 (Wire
uid 8903,0
shape (OrthoPolyLine
uid 8904,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "48000,97000,51000,97000"
pts [
"48000,97000"
"51000,97000"
]
)
start &260
end &87
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8905,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8906,0
va (VaSet
)
xt "42000,95800,47100,97000"
st "PCPlus4"
blo "42000,96800"
tm "WireNameMgr"
)
)
on &47
)
*322 (Wire
uid 8911,0
shape (OrthoPolyLine
uid 8912,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "56000,85000,177250,105000"
pts [
"56000,97000"
"61000,97000"
"61000,105000"
"168000,105000"
"168000,85000"
"177250,85000"
]
)
start &88
end &191
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 8913,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8914,0
va (VaSet
)
xt "168000,83800,178700,85000"
st "PCPlus4_UlogVec"
blo "168000,84800"
tm "WireNameMgr"
)
s (Text
uid 8979,0
va (VaSet
)
xt "168000,85000,168000,85000"
blo "168000,85000"
tm "SignalTypeMgr"
)
)
on &92
)
*323 (Wire
uid 9096,0
shape (OrthoPolyLine
uid 9097,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "166750,83000,177250,83000"
pts [
"166750,83000"
"177250,83000"
]
)
start &249
end &189
sat 32
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 9098,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9099,0
va (VaSet
)
xt "168750,81800,174050,83000"
st "readData"
blo "168750,82800"
tm "WireNameMgr"
)
)
on &93
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *324 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*325 (Text
uid 42,0
va (VaSet
font "Verdana,9,1"
)
xt "0,0,7600,1200"
st "Package List"
blo "0,1000"
)
*326 (MLText
uid 43,0
va (VaSet
)
xt "0,1200,17500,7200"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
LIBRARY gates;
USE gates.gates.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*327 (Text
uid 45,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,0,30800,1200"
st "Compiler Directives"
blo "20000,1000"
)
*328 (Text
uid 46,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,1200,33100,2400"
st "Pre-module directives:"
blo "20000,2200"
)
*329 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2400,32100,4800"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*330 (Text
uid 48,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,4800,33700,6000"
st "Post-module directives:"
blo "20000,5800"
)
*331 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*332 (Text
uid 50,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,6000,33200,7200"
st "End-module directives:"
blo "20000,7000"
)
*333 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,7200,20000,7200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-2771,-2892,213843,111249"
cachedDiagramExtent "0,0,199500,112800"
pageSetupInfo (PageSetupInfo
ptrCmd "Adobe PDF,winspool,"
fileName "Documents\\*.pdf"
toPrinter 1
colour 1
xMargin 48
yMargin 48
paperWidth 1077
paperHeight 761
windowsPaperWidth 1077
windowsPaperHeight 761
paperType "A4"
windowsPaperName "A4"
windowsPaperType 9
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
bestFit 1
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 10032,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "500,2150,1400,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,9,1"
)
xt "1000,1000,5000,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*334 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,3200,6700,4400"
st "<library>"
blo "1300,4200"
tm "BdLibraryNameMgr"
)
*335 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,4400,6100,5600"
st "<block>"
blo "1300,5400"
tm "BlkNameMgr"
)
*336 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,5600,3800,6800"
st "U_0"
blo "1300,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "1300,13200,1300,13200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*337 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,3200,3750,4400"
st "Library"
blo "-350,4200"
)
*338 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,4400,8350,5600"
st "MWComponent"
blo "-350,5400"
)
*339 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,5600,2150,6800"
st "U_0"
blo "-350,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7350,1200,-7350,1200"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*340 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,3200,4100,4400"
st "Library"
blo "0,4200"
tm "BdLibraryNameMgr"
)
*341 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,4400,8000,5600"
st "SaComponent"
blo "0,5400"
tm "CptNameMgr"
)
*342 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,5600,2500,6800"
st "U_0"
blo "0,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7000,1200,-7000,1200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1000,0,9000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*343 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,3200,3600,4400"
st "Library"
blo "-500,4200"
)
*344 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,4400,8500,5600"
st "VhdlComponent"
blo "-500,5400"
)
*345 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,5600,2000,6800"
st "U_0"
blo "-500,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7500,1200,-7500,1200"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1650,0,9650,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Verdana,9,1"
)
xt "-1150,3200,2950,4400"
st "Library"
blo "-1150,4200"
)
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va (VaSet
font "Verdana,9,1"
)
xt "-1150,4400,9150,5600"
st "VerilogComponent"
blo "-1150,5400"
)
*348 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-1150,5600,1350,6800"
st "U_0"
blo "-1150,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-8150,1200,-8150,1200"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Verdana,9,1"
)
xt "2800,3800,5200,5000"
st "eb1"
blo "2800,4800"
tm "HdlTextNameMgr"
)
*350 (Text
va (VaSet
font "Verdana,9,1"
)
xt "2800,5000,4000,6200"
st "1"
blo "2800,6000"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Verdana,9,1"
)
xt "-650,-600,650,600"
st "G"
blo "-650,400"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
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]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2900,1200"
st "sig0"
blo "0,1000"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,3800,1200"
st "dbus0"
blo "0,1000"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,4700,1200"
st "bundle0"
blo "0,1000"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1200,1500,2400"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1300,18500,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
)
xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*351 (Text
va (VaSet
font "Verdana,9,1"
)
xt "11200,20000,22000,21200"
st "Frame Declarations"
blo "11200,21000"
)
*352 (MLText
va (VaSet
)
xt "11200,21200,11200,21200"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1300,11000,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
)
xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*353 (Text
va (VaSet
font "Verdana,9,1"
)
xt "11200,20000,22000,21200"
st "Frame Declarations"
blo "11200,21000"
)
*354 (MLText
va (VaSet
)
xt "11200,21200,11200,21200"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,0,27400,1200"
st "Declarations"
blo "20000,1000"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,1200,23700,2400"
st "Ports:"
blo "20000,2200"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,7200,25200,8400"
st "Pre User:"
blo "20000,8200"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,8400,47500,19600"
st "constant c_dataWidth : positive := g_dataWidth;
constant c_bramAddrWidth : positive := 10;

constant c_tPC : time := 40 ps;
constant c_tSetup : time := 50 ps;
constant c_tMux : time := 30 ps;
constant c_tALU : time := 120 ps;
constant c_tDec : time := 25 ps;
constant c_tExt : time := 35 ps;
constant c_tMemRd : time := 200 ps;
constant c_tMemWr : time := 60 ps;
constant c_tRfRd : time := 100 ps;
constant c_tRfWr : time := 60 ps;
constant c_tAdd : time := 100 ps;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,19600,29500,20800"
st "Diagram Signals:"
blo "20000,20600"
)
postUserLabel (Text
uid 7,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,40000,26400,41200"
st "Post User:"
blo "20000,41000"
)
postUserText (MLText
uid 8,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,32400,40000,33200"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 139,0
usingSuid 1
emptyRow *355 (LEmptyRow
)
uid 54,0
optionalChildren [
*356 (RefLabelRowHdr
)
*357 (TitleRowHdr
)
*358 (FilterRowHdr
)
*359 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*360 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*361 (GroupColHdr
tm "GroupColHdrMgr"
)
*362 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*363 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*364 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*365 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*366 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*367 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*368 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 4
suid 20,0
)
)
uid 676,0
)
*369 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 2
suid 21,0
)
)
uid 678,0
)
*370 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "zero"
t "std_ulogic"
o 30
suid 46,0
)
)
uid 1364,0
)
*371 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 downto 0)"
o 26
suid 48,0
)
)
uid 1438,0
)
*372 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 7
suid 50,0
)
)
uid 1440,0
)
*373 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 19
suid 57,0
)
)
uid 1446,0
)
*374 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "regwrite"
t "std_ulogic"
o 24
suid 58,0
)
)
uid 1448,0
)
*375 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "instruction"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 20
suid 59,0
)
)
uid 1664,0
)
*376 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "immExt"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 18
suid 65,0
)
)
uid 2124,0
)
*377 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "srcA"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 27
suid 74,0
)
)
uid 2454,0
)
*378 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "srcB"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 28
suid 75,0
)
)
uid 2456,0
)
*379 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "ALUResult"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 8
suid 79,0
)
)
uid 2771,0
)
*380 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "dbg_leds"
t "std_ulogic_vector"
b "(31 DOWNTO 0)"
o 5
suid 93,0
)
)
uid 4371,0
)
*381 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 97,0
)
)
uid 4506,0
)
*382 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "btns"
t "std_ulogic_vector"
b "(g_btnsNb-1 DOWNTO 0)"
o 1
suid 101,0
)
)
uid 5859,0
)
*383 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "leds"
t "std_ulogic_vector"
b "(g_dataWidth-1 DOWNTO 0)"
o 6
suid 102,0
)
)
uid 5861,0
)
*384 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "PCTarget"
t "unsigned"
b "(c_dataWidth - 1 downto 0)"
o 15
suid 103,0
)
)
uid 7215,0
)
*385 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "PCPlus4"
t "unsigned"
b "(c_dataWidth - 1 downto 0)"
o 12
suid 104,0
)
)
uid 7217,0
)
*386 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PCNext"
t "unsigned"
b "(c_dataWidth-1 DOWNTO 0)"
o 11
suid 105,0
)
)
uid 7219,0
)
*387 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PCSrc"
t "std_uLogic"
o 14
suid 107,0
)
)
uid 7221,0
)
*388 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "PC"
t "unsigned"
b "(c_dataWidth - 1 DOWNTO 0)"
o 10
suid 109,0
)
)
uid 7223,0
)
*389 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "writeData"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 29
suid 113,0
)
)
uid 7410,0
)
*390 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "out1"
t "unsigned"
b "(c_dataWidth-1 DOWNTO 0)"
o 22
suid 114,0
)
)
uid 7412,0
)
*391 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ALUSrc"
t "std_uLogic"
o 9
suid 116,0
)
)
uid 7478,0
)
*392 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "memWrite"
t "std_ulogic"
o 21
suid 118,0
)
)
uid 7480,0
)
*393 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "result"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 25
suid 126,0
)
)
uid 7634,0
)
*394 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "c_fourUnsigned"
t "unsigned"
b "(c_dataWidth-1 DOWNTO 0)"
o 16
suid 131,0
i "to_unsigned(4, c_dataWidth)"
)
)
uid 8705,0
)
*395 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "c_zeroUlogVec"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 17
suid 135,0
i "(others=>'0')"
)
)
uid 8881,0
)
*396 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PCPlus4_UlogVec"
t "std_ulogic_vector"
b "(c_dataWidth - 1 downto 0)"
o 13
suid 138,0
)
)
uid 8919,0
)
*397 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "readData"
t "std_ulogic_vector"
b "(c_dataWidth-1 DOWNTO 0)"
o 30
suid 139,0
)
)
uid 9100,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*398 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *399 (MRCItem
litem &355
pos 30
dimension 20
)
uid 69,0
optionalChildren [
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litem &356
pos 0
dimension 20
uid 70,0
)
*401 (MRCItem
litem &357
pos 1
dimension 23
uid 71,0
)
*402 (MRCItem
litem &358
pos 2
hidden 1
dimension 20
uid 72,0
)
*403 (MRCItem
litem &368
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