30 lines
731 B
VHDL
30 lines
731 B
VHDL
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ARCHITECTURE masterVersion OF DAC IS
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signal parallelIn1: unsigned(parallelIn'range);
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signal integrator: unsigned(parallelIn'high+1 downto 0);
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signal quantized: std_ulogic;
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BEGIN
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-- parallelIn1 <= parallelIn;
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parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2);
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integrate: process(reset, clock)
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begin
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if reset = '1' then
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integrator <= (others => '0');
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elsif rising_edge(clock) then
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if quantized = '0' then
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integrator <= integrator + parallelIn1;
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else
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integrator <= integrator + parallelIn1 - 2**parallelIn'length;
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end if;
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end if;
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end process integrate;
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quantized <= integrator(integrator'high);
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serialOut <= quantized;
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END ARCHITECTURE masterVersion;
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