60 lines
2.1 KiB
VHDL
60 lines
2.1 KiB
VHDL
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ARCHITECTURE order2_masterVersion OF DAC IS
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constant attenuationShift: positive := 3;
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constant acc1BitNb: positive := parallelIn'length+5;
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constant acc2BitNb: positive := parallelIn'length+5;
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signal parallelIn1, parallelIn2: signed(parallelIn'high downto 0);
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signal acc1: signed(acc1BitNb-1 downto 0);
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signal acc2: signed(acc2BitNb-1 downto 0);
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constant c1: signed(acc1'range)
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:= shift_left(to_signed(1, acc1'length), parallelIn'length-1);
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constant c2: signed(acc2'range)
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:= resize(shift_left(c1, 4), acc2'length);
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signal quantized: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- offset input to signed values
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parallelIn1(parallelIn1'high) <= not parallelIn(parallelIn'high);
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parallelIn1(parallelIn1'high-1 downto 0) <=
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signed(parallelIn(parallelIn'high-1 downto 0));
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-- attenuate signal
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parallelIn2 <= parallelIn1 - shift_right(parallelIn1, attenuationShift);
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------------------------------------------------------------------------------
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-- SD integrators
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integrate1: process(reset, clock)
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begin
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if reset = '1' then
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acc1 <= (others => '0');
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elsif rising_edge(clock) then
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if quantized = '1' then
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acc1 <= acc1 + resize(parallelIn2, acc1'length) - c1;
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else
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acc1 <= acc1 + resize(parallelIn2, acc1'length) + c1;
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end if;
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end if;
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end process integrate1;
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integrate2: process(reset, clock)
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begin
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if reset = '1' then
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acc2 <= (others => '0');
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elsif rising_edge(clock) then
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if quantized = '1' then
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acc2 <= acc2 + resize(acc1, acc2'length) - c2;
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else
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acc2 <= acc2 + resize(acc1, acc2'length) + c2;
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end if;
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end if;
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end process integrate2;
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------------------------------------------------------------------------------
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-- test last integrator output
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quantized <= '1' when acc2 >= 0 else '0';
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serialOut <= quantized;
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END ARCHITECTURE order2_masterVersion;
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