22 lines
451 B
VHDL
22 lines
451 B
VHDL
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ARCHITECTURE RTL OF scratchpad IS
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subtype memoryWordType is signed(dataOut'range);
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type memoryArrayType is array (0 to 2**addr'length-1) of memoryWordType;
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signal memoryArray : memoryArrayType;
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BEGIN
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process (clock)
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begin
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if rising_edge(clock) then
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if write = '1' then
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memoryArray(to_integer(addr)) <= dataIn;
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end if;
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end if;
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end process;
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dataOut <= memoryArray(to_integer(addr));
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END ARCHITECTURE RTL;
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