41 lines
1.4 KiB
VHDL
41 lines
1.4 KiB
VHDL
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ARCHITECTURE RTL OF branchStack IS
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subtype progCounterType is unsigned(progCounter'range);
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type progCounterArrayType is array (0 to 2**stackPointerBitNb) of progCounterType;
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signal progCounterArray : progCounterArrayType;
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signal writePointer : unsigned(stackPointerBitNb-1 downto 0);
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signal readPointer : unsigned(stackPointerBitNb-1 downto 0);
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BEGIN
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------------------------------------------------------------------------------
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-- stack pointers
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updateStackPointer: process(reset, clock)
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begin
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if reset = '1' then
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writePointer <= (others => '0');
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elsif rising_edge(clock) then
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if storePC = '1' then
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writePointer <= writePointer + 1;
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elsif prevPC = '1' then
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writePointer <= writePointer - 1;
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end if;
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end if;
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end process updateStackPointer;
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readPointer <= writePointer - 1;
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------------------------------------------------------------------------------
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-- program counters stack
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updateStack: process(reset, clock)
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begin
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if rising_edge(clock) then
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if storePc = '1' then
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progCounterArray(to_integer(writePointer)) <= progCounter;
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end if;
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storedProgCounter <= progCounterArray(to_integer(readPointer));
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end if;
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end process updateStack;
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END ARCHITECTURE RTL;
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