27 lines
578 B
Plaintext
27 lines
578 B
Plaintext
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-- VHDL Entity SplineInterpolator.resizer.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:36 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY resizer IS
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GENERIC(
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inputBitNb : positive := 16;
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outputBitNb : positive := 16
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);
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PORT(
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resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
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resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END resizer ;
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