32 lines
835 B
Plaintext
32 lines
835 B
Plaintext
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-- VHDL Entity SplineInterpolator.sineGen.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:40 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY sineGen IS
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GENERIC(
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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step : IN unsigned (phaseBitNb-1 DOWNTO 0);
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sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
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sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
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square : OUT unsigned (signalBitNb-1 DOWNTO 0);
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triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END sineGen ;
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