50 lines
1.6 KiB
VHDL
50 lines
1.6 KiB
VHDL
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE RTL OF uvmAhbMonitor IS
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signal addressReg: unsigned(hAddr'range);
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signal writeReg: std_ulogic;
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signal readReg: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- register address and controls
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storeControls: process(hReset_n, hClk)
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begin
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if not(hReset_n) = '1' then
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addressReg <= (others => '0');
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writeReg <= '0';
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readReg <= '0';
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elsif rising_edge(hClk) then
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writeReg <= '0';
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readReg <= '0';
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if (hSel = '1') and (hTrans = transNonSeq) then
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addressReg <= hAddr(addressReg'range);
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writeReg <= hWrite;
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readReg <= not hWrite;
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end if;
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end if;
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end process storeControls;
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-- monitor acesses
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reportBusAccess: process(hReset_n, hClk)
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begin
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if not(hReset_n) = '1' then
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monitorTransaction <= pad( false, ' ', monitorTransaction'length, "idle");
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elsif rising_edge(hClk) then
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if readReg = '1' then
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monitorTransaction <= pad(
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false, ' ', monitorTransaction'length,
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"read " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hRData)
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);
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elsif writeReg = '1' then
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monitorTransaction <= pad(
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false, ' ', monitorTransaction'length,
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"written " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hWData)
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);
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end if;
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end if;
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end process reportBusAccess;
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END ARCHITECTURE RTL;
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