1
0
SEm-Labos/Libs/Memory/hds/bram@Bin@ASCII@Init/symbol.sb

1772 lines
22 KiB
Plaintext
Raw Normal View History

2024-02-23 13:01:05 +00:00
DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
libraryRefs [
"ieee"
]
)
version "27.1"
appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 14,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 151,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
uid 51,0
)
*15 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "writeEn"
t "std_ulogic"
o 3
suid 4,0
)
)
uid 57,0
)
*16 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "addressIn"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 4
suid 5,0
)
)
uid 59,0
)
*17 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 5
suid 6,0
)
)
uid 61,0
)
*18 (LogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
posAdd 0
o 6
suid 7,0
)
)
uid 63,0
)
*19 (LogPort
port (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 3,0
)
)
uid 55,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 164,0
optionalChildren [
*20 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *21 (MRCItem
litem &1
pos 6
dimension 20
)
uid 166,0
optionalChildren [
*22 (MRCItem
litem &2
pos 0
dimension 20
uid 167,0
)
*23 (MRCItem
litem &3
pos 1
dimension 23
uid 168,0
)
*24 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 169,0
)
*25 (MRCItem
litem &14
pos 0
dimension 20
uid 52,0
)
*26 (MRCItem
litem &15
pos 2
dimension 20
uid 58,0
)
*27 (MRCItem
litem &16
pos 3
dimension 20
uid 60,0
)
*28 (MRCItem
litem &17
pos 4
dimension 20
uid 62,0
)
*29 (MRCItem
litem &18
pos 5
dimension 20
uid 64,0
)
*30 (MRCItem
litem &19
pos 1
dimension 20
uid 56,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 170,0
optionalChildren [
*31 (MRCItem
litem &5
pos 0
dimension 20
uid 171,0
)
*32 (MRCItem
litem &7
pos 1
dimension 50
uid 172,0
)
*33 (MRCItem
litem &8
pos 2
dimension 100
uid 173,0
)
*34 (MRCItem
litem &9
pos 3
dimension 50
uid 174,0
)
*35 (MRCItem
litem &10
pos 4
dimension 100
uid 175,0
)
*36 (MRCItem
litem &11
pos 5
dimension 100
uid 176,0
)
*37 (MRCItem
litem &12
pos 6
dimension 50
uid 177,0
)
*38 (MRCItem
litem &13
pos 7
dimension 80
uid 178,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 165,0
vaOverrides [
]
)
]
)
uid 150,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *39 (LEmptyRow
)
uid 180,0
optionalChildren [
*40 (RefLabelRowHdr
)
*41 (TitleRowHdr
)
*42 (FilterRowHdr
)
*43 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*44 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*45 (GroupColHdr
tm "GroupColHdrMgr"
)
*46 (NameColHdr
tm "GenericNameColHdrMgr"
)
*47 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*48 (InitColHdr
tm "GenericValueColHdrMgr"
)
*49 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*50 (EolColHdr
tm "GenericEolColHdrMgr"
)
*51 (LogGeneric
generic (GiElement
name "addressBitNb"
type "positive"
value "8"
)
uid 439,0
)
*52 (LogGeneric
generic (GiElement
name "dataBitNb"
type "positive"
value "8"
)
uid 441,0
)
*53 (LogGeneric
generic (GiElement
name "initFile"
type "string"
value "\"bramInit.txt\""
)
uid 443,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 192,0
optionalChildren [
*54 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *55 (MRCItem
litem &39
pos 3
dimension 20
)
uid 194,0
optionalChildren [
*56 (MRCItem
litem &40
pos 0
dimension 20
uid 195,0
)
*57 (MRCItem
litem &41
pos 1
dimension 23
uid 196,0
)
*58 (MRCItem
litem &42
pos 2
hidden 1
dimension 20
uid 197,0
)
*59 (MRCItem
litem &51
pos 0
dimension 20
uid 440,0
)
*60 (MRCItem
litem &52
pos 1
dimension 20
uid 442,0
)
*61 (MRCItem
litem &53
pos 2
dimension 20
uid 444,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 198,0
optionalChildren [
*62 (MRCItem
litem &43
pos 0
dimension 20
uid 199,0
)
*63 (MRCItem
litem &45
pos 1
dimension 50
uid 200,0
)
*64 (MRCItem
litem &46
pos 2
dimension 100
uid 201,0
)
*65 (MRCItem
litem &47
pos 3
dimension 100
uid 202,0
)
*66 (MRCItem
litem &48
pos 4
dimension 86
uid 203,0
)
*67 (MRCItem
litem &49
pos 5
dimension 50
uid 204,0
)
*68 (MRCItem
litem &50
pos 6
dimension 80
uid 205,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 193,0
vaOverrides [
]
)
]
)
uid 179,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init"
)
(vvPair
variable "d_logical"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init"
)
(vvPair
variable "date"
value "11.10.2022"
)
(vvPair
variable "day"
value "mar."
)
(vvPair
variable "day_long"
value "mardi"
)
(vvPair
variable "dd"
value "11"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "bramBinASCIIInit"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "11.10.2022"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "15:51:22"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Memory"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/CAr/Libraries/Memory/work"
)
(vvPair
variable "mm"
value "10"
)
(vvPair
variable "module_name"
value "bramBinASCIIInit"
)
(vvPair
variable "month"
value "oct."
)
(vvPair
variable "month_long"
value "octobre"
)
(vvPair
variable "p"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\dev\\car-labs\\hdl\\Libs\\Memory\\hds\\bram@Bin@ASCII@Init\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "15:51:22"
)
(vvPair
variable "unit"
value "bramBinASCIIInit"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2022"
)
(vvPair
variable "yy"
value "22"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 149,0
optionalChildren [
*69 (SymbolBody
uid 8,0
optionalChildren [
*70 (CptPort
uid 79,0
ps "OnEdgeStrategy"
shape (Triangle
uid 80,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,26625,39000,27375"
)
tg (CPTG
uid 81,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 82,0
va (VaSet
)
xt "40000,26500,43400,27700"
st "clock"
blo "40000,27500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 83,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,9200,15100,10200"
st "clock : IN std_ulogic ;"
)
thePort (LogicalPort
lang 11
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*71 (CptPort
uid 89,0
ps "OnEdgeStrategy"
shape (Triangle
uid 90,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,24625,39000,25375"
)
tg (CPTG
uid 91,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 92,0
va (VaSet
)
xt "40000,24500,41900,25700"
st "en"
blo "40000,25500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 93,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,10100,15000,11100"
st "en : IN std_ulogic ;"
)
thePort (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 3,0
)
)
)
*72 (CptPort
uid 94,0
ps "OnEdgeStrategy"
shape (Triangle
uid 95,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,20625,39000,21375"
)
tg (CPTG
uid 96,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 97,0
va (VaSet
)
xt "40000,20500,44400,21700"
st "writeEn"
blo "40000,21500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 98,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,11000,15500,12000"
st "writeEn : IN std_ulogic ;"
)
thePort (LogicalPort
lang 11
decl (Decl
n "writeEn"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*73 (CptPort
uid 99,0
ps "OnEdgeStrategy"
shape (Triangle
uid 100,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,14625,39000,15375"
)
tg (CPTG
uid 101,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 102,0
va (VaSet
)
xt "40000,14500,45800,15700"
st "addressIn"
blo "40000,15500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 103,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,11900,31000,12900"
st "addressIn : IN std_ulogic_vector (addressBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
lang 11
decl (Decl
n "addressIn"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 4
suid 5,0
)
)
)
*74 (CptPort
uid 104,0
ps "OnEdgeStrategy"
shape (Triangle
uid 105,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,18625,39000,19375"
)
tg (CPTG
uid 106,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 107,0
va (VaSet
)
xt "40000,18500,44000,19700"
st "dataIn"
blo "40000,19500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 108,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,12800,29300,13800"
st "dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
)
thePort (LogicalPort
lang 11
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 5
suid 6,0
)
)
)
*75 (CptPort
uid 109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 206,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,16625,39000,17375"
)
tg (CPTG
uid 111,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 112,0
va (VaSet
)
xt "40000,16500,44800,17700"
st "dataOut"
blo "40000,17500"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 113,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,13700,29400,14700"
st "dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0)"
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
posAdd 0
o 6
suid 7,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "39000,11000,55000,29000"
)
oxt "15000,6000,33000,36000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Verdana,8,1"
)
xt "39200,29000,43400,30000"
st "Memory"
blo "39200,29800"
)
second (Text
uid 12,0
va (VaSet
font "Verdana,8,1"
)
xt "39200,30000,42100,31000"
st "bramBinASCIIInit"
blo "39200,30800"
)
)
gi *76 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Verdana,8,0"
)
xt "39000,32000,54400,37000"
st "Generic Declarations
addressBitNb positive 8
dataBitNb positive 8
initFile string \"bramInit.txt\"
"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "8"
)
(GiElement
name "dataBitNb"
type "positive"
value "8"
)
(GiElement
name "initFile"
type "string"
value "\"bramInit.txt\""
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sIVOD 1
)
portVis (PortSigDisplay
sTC 0
sIVOD 1
)
)
*77 (Grouping
uid 16,0
optionalChildren [
*78 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,48000,53000,49000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48500,36200,48500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*79 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,44000,57000,45000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44500,53200,44500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*80 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,46000,53000,47000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46500,36200,46500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*81 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,46000,36000,47000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46500,32200,46500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*82 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,45000,73000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,67300,46400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*83 (CommentText
uid 33,0
shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,44000,73000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44500,57200,44500"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*84 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,44000,53000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
)
xt "37350,44400,47650,45600"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*85 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,47000,36000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 41,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47500,32200,47500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*86 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,48000,36000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48500,32200,48500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*87 (CommentText
uid 45,0
shape (Rectangle
uid 46,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,47000,53000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47500,36200,47500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 17,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,44000,73000,49000"
)
oxt "14000,66000,55000,71000"
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *88 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
*89 (Text
uid 49,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*90 (MLText
uid 50,0
va (VaSet
)
xt "0,1000,18100,4600"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
windowSize "108,40,1411,907"
viewArea "-1100,-1100,69850,45826"
cachedDiagramExtent "0,0,73000,49000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
xMargin 49
yMargin 49
unixPaperWidth 595
unixPaperHeight 842
paperType "A4"
unixPaperName "A4 (210mm x 297mm)"
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
libraryName ""
entityName ""
viewName ""
)
defaultSymbolBody (SymbolBody
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,33000,26000"
)
biTextGroup (BiTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "Verdana,8,1"
)
xt "22200,15000,25800,16000"
st "<library>"
blo "22200,15800"
)
second (Text
va (VaSet
font "Verdana,8,1"
)
xt "22200,16000,24800,17000"
st "<cell>"
blo "22200,16800"
)
)
gi *91 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Verdana,8,0"
)
xt "0,12000,9700,13000"
st "Generic Declarations"
)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sIVOD 1
)
)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "Verdana,8,0"
)
xt "0,750,1500,1650"
st "In0"
blo "0,1450"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Verdana,8,0"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
bg "0,0,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "Verdana,8,0"
)
xt "0,750,3500,1650"
st "Buffer0"
blo "0,1450"
tm "CptPortNameMgr"
)
)
dt (MLText
va (VaSet
font "Verdana,8,0"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Buffer0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
)
)
)
DeclarativeBlock *92 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,7400,7000,8400"
st "Declarations"
blo "0,8200"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,8300,3400,9300"
st "Ports:"
blo "0,9100"
)
externalLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,14600,3000,15600"
st "User:"
blo "0,15400"
)
internalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,7400,7600,8400"
st "Internal User:"
blo "0,8200"
)
externalText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,15500,2000,15500"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,7400,0,7400"
tm "SyDeclarativeTextMgr"
)
)
lastUid 676,0
activeModelName "Symbol:GEN"
)