1503 lines
19 KiB
Plaintext
1503 lines
19 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 10
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 12,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 74,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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||
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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|
*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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|
*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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|
*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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|
*11 (BoundsColHdr
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|
tm "BoundsColHdrMgr"
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)
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|
*12 (InitColHdr
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|
tm "InitColHdrMgr"
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|
)
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|
*13 (EolColHdr
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tm "EolColHdrMgr"
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|
)
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|
*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 10,0
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)
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)
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|
uid 303,0
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)
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*15 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "countOut"
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|
t "unsigned"
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|
b "(counterBitNb-1 downto 0)"
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|
o 2
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suid 11,0
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)
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)
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uid 305,0
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)
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*16 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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|
n "reset"
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|
t "std_ulogic"
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|
o 3
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suid 12,0
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)
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)
|
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|
uid 307,0
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||
|
)
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]
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||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 87,0
|
||
|
optionalChildren [
|
||
|
*17 (Sheet
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||
|
sheetRow (SheetRow
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|
headerVa (MVa
|
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|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
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|
cellVa (MVa
|
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|
cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
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|
groupVa (MVa
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|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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|
emptyMRCItem *18 (MRCItem
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|
litem &1
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pos 3
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dimension 20
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)
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uid 89,0
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optionalChildren [
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*19 (MRCItem
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|
litem &2
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pos 0
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dimension 20
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uid 90,0
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)
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*20 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 91,0
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)
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*21 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 92,0
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)
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*22 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 304,0
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)
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*23 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 306,0
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)
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*24 (MRCItem
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litem &16
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pos 2
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|
dimension 20
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|
uid 308,0
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|
)
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]
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|
)
|
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|
sheetCol (SheetCol
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|
propVa (MVa
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||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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|
textAngle 90
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)
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|
uid 93,0
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|
optionalChildren [
|
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|
*25 (MRCItem
|
||
|
litem &5
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|
pos 0
|
||
|
dimension 20
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|
uid 94,0
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||
|
)
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|
*26 (MRCItem
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|
litem &7
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|
pos 1
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|
dimension 50
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|
uid 95,0
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|
)
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|
*27 (MRCItem
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||
|
litem &8
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||
|
pos 2
|
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|
dimension 100
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|
uid 96,0
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||
|
)
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|
*28 (MRCItem
|
||
|
litem &9
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||
|
pos 3
|
||
|
dimension 50
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||
|
uid 97,0
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||
|
)
|
||
|
*29 (MRCItem
|
||
|
litem &10
|
||
|
pos 4
|
||
|
dimension 100
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||
|
uid 98,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &11
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 99,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &12
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 100,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &13
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 101,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 88,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 73,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *33 (LEmptyRow
|
||
|
)
|
||
|
uid 103,0
|
||
|
optionalChildren [
|
||
|
*34 (RefLabelRowHdr
|
||
|
)
|
||
|
*35 (TitleRowHdr
|
||
|
)
|
||
|
*36 (FilterRowHdr
|
||
|
)
|
||
|
*37 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*38 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*39 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*40 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*41 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*42 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*43 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*44 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*45 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "counterBitNb"
|
||
|
type "positive"
|
||
|
value "32"
|
||
|
)
|
||
|
uid 152,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
displayShortBounds 1
|
||
|
editShortBounds 1
|
||
|
uid 115,0
|
||
|
optionalChildren [
|
||
|
*46 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *47 (MRCItem
|
||
|
litem &33
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 117,0
|
||
|
optionalChildren [
|
||
|
*48 (MRCItem
|
||
|
litem &34
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 118,0
|
||
|
)
|
||
|
*49 (MRCItem
|
||
|
litem &35
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 119,0
|
||
|
)
|
||
|
*50 (MRCItem
|
||
|
litem &36
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 120,0
|
||
|
)
|
||
|
*51 (MRCItem
|
||
|
litem &45
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 153,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 121,0
|
||
|
optionalChildren [
|
||
|
*52 (MRCItem
|
||
|
litem &37
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 122,0
|
||
|
)
|
||
|
*53 (MRCItem
|
||
|
litem &39
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 123,0
|
||
|
)
|
||
|
*54 (MRCItem
|
||
|
litem &40
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 124,0
|
||
|
)
|
||
|
*55 (MRCItem
|
||
|
litem &41
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 125,0
|
||
|
)
|
||
|
*56 (MRCItem
|
||
|
litem &42
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 126,0
|
||
|
)
|
||
|
*57 (MRCItem
|
||
|
litem &43
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 127,0
|
||
|
)
|
||
|
*58 (MRCItem
|
||
|
litem &44
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 128,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 116,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 102,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "asm_file"
|
||
|
value "beamer.asm"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_%(view)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "02/17/2020"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "Mon"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "Monday"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "17"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "pipelineCounter_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_author"
|
||
|
value "zas"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_date"
|
||
|
value "02/17/2020"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_host"
|
||
|
value "ZELL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "graphical_source_time"
|
||
|
value "17:11:08"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "ZELL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "PipelinedOperators_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/PipelinedOperators_test"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "02"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "pipelineCounter_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "Feb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "February"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tester\\interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_AsmPath"
|
||
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "/usr/opt/Modelsim/modeltech/bin"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "17:11:08"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "pipelineCounter_tester"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "zas"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2019.2 (Build 5)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "interface"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2020"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "20"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "Vhdl2002LangMgr"
|
||
|
uid 72,0
|
||
|
optionalChildren [
|
||
|
*59 (SymbolBody
|
||
|
uid 8,0
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|
optionalChildren [
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||
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uid 288,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 289,0
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||
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va (VaSet
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||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
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|
||
|
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|
)
|
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|
tg (CPTG
|
||
|
uid 290,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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||
|
ju 2
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||
|
blo "23500,7000"
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tm "CptPortNameMgr"
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st "clock : OUT std_ulogic ;
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||
|
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|
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|
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|
||
|
thePort (LogicalPort
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||
|
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|
||
|
decl (Decl
|
||
|
n "clock"
|
||
|
t "std_ulogic"
|
||
|
o 1
|
||
|
suid 10,0
|
||
|
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|
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tg (CPTG
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uid 295,0
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ps "CptPortTextPlaceStrategy"
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|
ju 2
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|
blo "47500,7000"
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tm "CptPortNameMgr"
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thePort (LogicalPort
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|
decl (Decl
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|
n "countOut"
|
||
|
t "unsigned"
|
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|
b "(counterBitNb-1 downto 0)"
|
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|
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|
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|
suid 11,0
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uid 298,0
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ps "OnEdgeStrategy"
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uid 299,0
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va (VaSet
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tg (CPTG
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uid 300,0
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ps "CptPortTextPlaceStrategy"
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uid 301,0
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|
st "reset"
|
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|
ju 2
|
||
|
blo "25500,7000"
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|
tm "CptPortNameMgr"
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dt (MLText
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uid 302,0
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st "reset : OUT std_ulogic
|
||
|
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|
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|
)
|
||
|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
||
|
n "reset"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 12,0
|
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|
)
|
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|
)
|
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|
)
|
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|
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|
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|
shape (Rectangle
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uid 9,0
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|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
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|
lineColor "0,32896,0"
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|
lineWidth 2
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|
)
|
||
|
xt "15000,6000,55000,14000"
|
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|
)
|
||
|
biTextGroup (BiTextGroup
|
||
|
uid 10,0
|
||
|
ps "CenterOffsetStrategy"
|
||
|
stg "VerticalLayoutStrategy"
|
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|
first (Text
|
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|
uid 11,0
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|
va (VaSet
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font "Verdana,8,1"
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st "PipelinedOperators_test"
|
||
|
blo "28450,9850"
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|
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|
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|
second (Text
|
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|
uid 12,0
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va (VaSet
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font "Verdana,8,1"
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st "pipelineCounter_tester"
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|
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|
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|
gi *63 (GenericInterface
|
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|
uid 13,0
|
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|
ps "CenterOffsetStrategy"
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matrix (Matrix
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uid 14,0
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text (MLText
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|
|
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|
counterBitNb positive 32 "
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)
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|
header "Generic Declarations"
|
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|
showHdrWhenContentsEmpty 1
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)
|
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|
elements [
|
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|
(GiElement
|
||
|
name "counterBitNb"
|
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|
type "positive"
|
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|
value "32"
|
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|
)
|
||
|
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|
||
|
)
|
||
|
portInstanceVisAsIs 1
|
||
|
portInstanceVis (PortSigDisplay
|
||
|
sTC 0
|
||
|
sF 0
|
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|
)
|
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|
portVis (PortSigDisplay
|
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|
sTC 0
|
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|
sF 0
|
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|
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|
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|
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|
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*64 (Grouping
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|
uid 16,0
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