43 lines
1.4 KiB
VHDL
43 lines
1.4 KiB
VHDL
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-- restart -f ; run 34 ms
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ARCHITECTURE test OF serialPortTransmitter_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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-- Tx test
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constant rs232Frequency: real := baudRate;
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constant rs232Period: time := (1.0/rs232Frequency) * 1 sec;
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constant rs232WriteInterval: time := 20*rs232Period;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- Tx test
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process
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begin
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dataIn <= (others => '0');
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send <= '0';
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wait for rs232Period;
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for index in 0 to 2**dataBitNb-1 loop
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dataIn <= std_ulogic_vector(to_unsigned(index, dataIn'length));
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wait until rising_edge(clock_int);
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send <= '1';
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wait until rising_edge(clock_int);
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send <= '0';
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wait for rs232WriteInterval;
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end loop;
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wait;
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end process;
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END ARCHITECTURE test;
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