44 lines
902 B
VHDL
44 lines
902 B
VHDL
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ARCHITECTURE studentVersion OF pipelineCounter IS
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signal b : signed(countOut'range);
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signal sum : signed(countOut'range);
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COMPONENT pipelineAdder
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GENERIC (
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bitNb : positive := 32;
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stageNb : positive := 4
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);
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PORT (
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reset : IN std_ulogic;
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clock : IN std_ulogic;
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cIn : IN std_ulogic;
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a : IN signed (bitNb-1 DOWNTO 0);
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b : IN signed (bitNb-1 DOWNTO 0);
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sum : OUT signed (bitNb-1 DOWNTO 0);
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cOut : OUT std_ulogic
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);
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END COMPONENT;
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BEGIN
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b <= to_signed(1, b'length);
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adder: pipelineAdder
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GENERIC MAP (
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bitNb => countOut'length,
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stageNb => stageNb
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)
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PORT MAP (
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reset => reset,
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clock => clock,
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cIn => '0',
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a => sum,
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b => b,
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sum => sum,
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cOut => open
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);
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countOut <= unsigned(sum);
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END ARCHITECTURE studentVersion;
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