45 lines
1.4 KiB
VHDL
45 lines
1.4 KiB
VHDL
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USE std.textio.all;
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ARCHITECTURE Spartan3E OF blockRAM IS
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subtype registerType is std_ulogic_vector(dataBitNb-1 downto 0);
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type memoryType is array (0 to 2**addressBitNb-1) of registerType;
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-- Define function to create initvalue signal
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impure function ReadRamContentFromFile(ramContentFileSpec : in string) return memoryType is
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FILE ramContentFile : text open read_mode is ramContentFileSpec;
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variable ramContentFileLine : line;
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variable ramContent : memoryType;
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variable ramCurrentWord : bit_vector(registerType'range);
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variable index : natural := 0; --241;
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begin
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for index in ramContent'range loop
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-- while not endfile(ramContentFile) loop
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readline(ramContentFile, ramContentFileLine);
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read(ramContentFileLine, ramCurrentWord);
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ramContent(index) := std_ulogic_vector(to_stdlogicvector(ramCurrentWord));
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-- index := index + 1;
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end loop;
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return ramContent;
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end function;
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shared variable memoryArray: memoryType := ReadRamContentFromFile(initFileSpec);
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BEGIN
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portA: process(clock)
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begin
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if rising_edge(clock) then
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if (en = '1') then
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if (write = '1') then
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memoryArray(to_integer(addr)) := dataIn;
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dataOut <= dataIn;
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else
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dataOut <= memoryArray(to_integer(addr));
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end if;
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end if;
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end if;
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end process portA;
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END ARCHITECTURE Spartan3E;
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