28 lines
820 B
VHDL
28 lines
820 B
VHDL
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ARCHITECTURE actel OF bram IS
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subtype ramCellType is std_ulogic_vector(dataBitNb-1 DOWNTO 0);
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type ramContentType is array(2**addressBitNb-1 downto 0) of ramCellType;
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signal ramContent: ramContentType ;
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BEGIN
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-- memory array
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process(clock)
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begin
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if rising_edge(clock) then
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if (en = '1') and (writeEn = '1') then
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ramContent(to_integer(unsigned(addressIn))) <= dataIn;
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end if;
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end if;
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end process;
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-- read register
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process(clock)
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begin
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if rising_edge(clock) then
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if en = '1' then
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dataOut <= ramContent(to_integer(unsigned(addressIn)));
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end if;
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end if;
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end process;
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END ARCHITECTURE actel;
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