33 lines
799 B
Plaintext
33 lines
799 B
Plaintext
|
-- VHDL Entity Memory.FIFO_bram.symbol
|
||
|
|
--
|
||
|
|
-- Created:
|
||
|
|
-- by - francois.francois (Aphelia)
|
||
|
|
-- at - 13:45:15 08/28/19
|
||
|
|
--
|
||
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||
|
|
--
|
||
|
|
LIBRARY ieee;
|
||
|
|
USE ieee.std_logic_1164.all;
|
||
|
|
USE ieee.numeric_std.all;
|
||
|
|
|
||
|
|
ENTITY FIFO_bram IS
|
||
|
|
GENERIC(
|
||
|
|
dataBitNb : positive := 8;
|
||
|
|
depth : positive := 8
|
||
|
|
);
|
||
|
|
PORT(
|
||
|
|
write : IN std_ulogic;
|
||
|
|
clock : IN std_ulogic;
|
||
|
|
reset : IN std_ulogic;
|
||
|
|
dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
|
||
|
|
read : IN std_ulogic;
|
||
|
|
dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0);
|
||
|
|
empty : OUT std_ulogic;
|
||
|
|
full : OUT std_ulogic
|
||
|
|
);
|
||
|
|
|
||
|
|
-- Declarations
|
||
|
|
|
||
|
|
END FIFO_bram ;
|
||
|
|
|