37 lines
1.6 KiB
VHDL
37 lines
1.6 KiB
VHDL
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ARCHITECTURE RTL OF sdramControllerBuildAddress IS
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constant addressPrecharge: std_ulogic_vector(memAddress'range)
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:= (10=> '1', others => '-');
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constant addressModeRegU : unsigned(memAddress'range)
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:= resize("0" & "00" & "010" & "0" & "000", memAddress'length);
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-- ll,10 = reserved,
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-- 9 = '0' programmed burst length => burst length applicable for both rd and wr
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-- 8,7 = Op mode = 00 => standard operation (all other states are reserved)
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-- 6,5,4 = CAS latency = 010 => cas latency of 2
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-- 3 = Burst Type = '0' => Sequential (not interleaved)
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-- 2,1,0 = Brust Length = 000 => brust length is 1
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constant addressModeReg : std_ulogic_vector(memAddress'range)
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:= std_ulogic_vector(addressModeRegU);
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BEGIN
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buildAddresses: process(ramAddr, addrSelPrecharge, addrSelModeReg, addrSelRow, addrSelCol)
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begin
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memBankAddress <= std_ulogic_vector(ramAddr(ramAddr'high downto ramAddr'high-memBankAddress'length+1));
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if addrSelPrecharge = '1' then
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memAddress <= addressPrecharge;
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elsif addrSelModeReg = '1' then
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memAddress <= addressModeReg;
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elsif addrSelRow = '1' then
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memAddress <= std_ulogic_vector(ramAddr(rowAddressBitNb+colAddressBitNb-1 downto colAddressBitNb));
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elsif addrSelCol = '1' then
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memAddress(memAddress'high downto colAddressBitNb) <= (others => '0');
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memAddress(10) <= '1';
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memAddress(colAddressBitNb-1 downto 0) <= std_ulogic_vector(ramAddr(colAddressBitNb-1 downto 0));
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else
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memAddress <= (others => '-');
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end if;
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end process buildAddresses;
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END ARCHITECTURE RTL;
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