340 lines
12 KiB
VHDL
340 lines
12 KiB
VHDL
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--LIBRARY std;
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-- USE std.textio.ALL;
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LIBRARY COMMON_TEST;
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USE COMMON_TEST.testUtils.all;
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ARCHITECTURE test OF fifo_tester IS
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constant clockFrequency: real := 66.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_ulogic := '1';
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constant testInterval: time := 10*clockPeriod;
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signal dataIn_int: integer;
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signal read_int: std_ulogic;
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signal dataOffset: integer;
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signal dataValid: std_ulogic;
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signal dataRead: integer;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- test sequence
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process
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variable readIndex: integer;
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begin
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write <= '0';
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read_int <= '0';
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dataOffset <= -16#10#;
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wait for 5*clockPeriod;
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print(
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lf & lf & lf &
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"----------------------------------------------------------------" & lf &
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"Starting testbench" & lf &
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lf & lf
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);
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--..........................................................................
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-- full write / read after end of write
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", full FIFO write direclty followed by full read" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1';
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for index in 0 to fifoDepth-1 loop
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dataIn_int <= dataOffset + index;
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wait for clockPeriod;
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end loop;
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write <= '0';
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-- read FIFO
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read_int <= '1';
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readIndex := 0;
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while empty = '0' loop
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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--..........................................................................
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-- full write / read after some time
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", full FIFO write and delay before read" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1';
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for index in 0 to fifoDepth-1 loop
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dataIn_int <= dataOffset + index;
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wait for clockPeriod;
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end loop;
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write <= '0';
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-- wait before read
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wait for 4*clockPeriod;
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-- read FIFO
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read_int <= '1';
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readIndex := 0;
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while empty = '0' loop
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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--..........................................................................
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-- write / read direct
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", full FIFO write with asynchronous direct read" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1', '0' after 8*clockPeriod;
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dataIn_int <= dataOffset + 16#00#,
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dataOffset + 16#01# after 1*clockPeriod,
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dataOffset + 16#02# after 2*clockPeriod,
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dataOffset + 16#03# after 3*clockPeriod,
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dataOffset + 16#04# after 4*clockPeriod,
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dataOffset + 16#05# after 5*clockPeriod,
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dataOffset + 16#06# after 6*clockPeriod,
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dataOffset + 16#07# after 7*clockPeriod;
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-- read FIFO
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wait until empty = '0';
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read_int <= '1';
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readIndex := -1;
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while empty = '0' loop
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if readIndex >= 0 then
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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end if;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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--..........................................................................
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-- write / read direct with clock period delay
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", full FIFO write with synchronous direct read" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1', '0' after 8*clockPeriod;
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dataIn_int <= dataOffset + 16#00#,
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dataOffset + 16#01# after 1*clockPeriod,
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dataOffset + 16#02# after 2*clockPeriod,
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dataOffset + 16#03# after 3*clockPeriod,
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dataOffset + 16#04# after 4*clockPeriod,
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dataOffset + 16#05# after 5*clockPeriod,
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dataOffset + 16#06# after 6*clockPeriod,
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dataOffset + 16#07# after 7*clockPeriod;
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-- read FIFO
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wait until empty = '0';
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wait until rising_edge(clock_int);
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read_int <= '1';
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readIndex := 0;
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while empty = '0' loop
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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--..........................................................................
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-- slow read sets FIFO full
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", slow reading sets FIFO full and requires waiting before writing on" &
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lf & lf
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);
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-- prepare slow FIFO reading
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wait until rising_edge(clock_int);
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wait for 2*clockPeriod;
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read_int <= '1' after 4*clockPeriod,
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'0' after 5*clockPeriod,
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'1' after 14*clockPeriod,
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'0' after 15*clockPeriod,
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'1' after 24*clockPeriod,
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'0' after 25*clockPeriod,
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'1' after 34*clockPeriod,
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'0' after 35*clockPeriod,
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'1' after 44*clockPeriod,
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'0' after (45+2*fifoDepth-5)*clockPeriod;
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-- write 2*FIFO depth
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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for index in 0 to 2*fifoDepth-1 loop
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dataIn_int <= dataOffset + index;
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if full = '1' then
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wait until full = '0';
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wait for clockPeriod/8;
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end if;
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write <= '1';
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wait until rising_edge(clock_int);
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write <= '0';
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end loop;
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--..........................................................................
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-- write over full
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", attempt to write after FIFO full" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1';
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for index in 0 to fifoDepth+3 loop
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dataIn_int <= dataOffset + index;
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wait for clockPeriod;
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end loop;
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write <= '0';
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--..........................................................................
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-- read FIFO once too much
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print(
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"At time " & sprintf("%9.3tu", now) &
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", attempt to read after FIFO empty" &
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lf & lf
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);
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read_int <= '1';
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wait for clockPeriod;
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wait until empty = '1';
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wait for clockPeriod;
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read_int <= '0';
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-- read when empty
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wait until rising_edge(clock_int);
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wait for 2*clockPeriod;
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read_int <= '1';
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wait for 2*clockPeriod;
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read_int <= '0';
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--..........................................................................
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-- read constantly
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", reading FIFO constantly (data valid when empty = '0')" &
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lf & lf
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);
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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read_int <= '1';
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wait for 2*clockPeriod;
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wait until rising_edge(clock_int);
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readIndex := -1;
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write <= '1';
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for index in 0 to fifoDepth-1 loop
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if empty = '0' then
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readIndex := readIndex + 1;
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end if;
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if (readIndex >= 0) and (empty = '0') then
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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end if;
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dataIn_int <= dataOffset + index;
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wait until rising_edge(clock_int);
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end loop;
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write <= '0';
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wait until empty = '1';
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wait for 2*clockPeriod;
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read_int <= '0';
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--..........................................................................
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-- full write / read with breaks
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wait for testInterval;
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print(
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"At time " & sprintf("%9.3tu", now) &
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", reading FIFO with breaks" &
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lf & lf
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);
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-- write FIFO
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dataOffset <= dataOffset + 16#10#;
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wait until rising_edge(clock_int);
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write <= '1';
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for index in 0 to fifoDepth-1 loop
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dataIn_int <= dataOffset + index;
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wait for clockPeriod;
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end loop;
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write <= '0';
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-- wait before read
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wait for 2*clockPeriod;
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-- read FIFO
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wait until rising_edge(clock_int);
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readIndex := 0;
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for index in 0 to fifoDepth/4-1 loop
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read_int <= '1';
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for rdIndex in 1 to 2 loop
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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wait for 2*clockPeriod;
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end loop;
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read_int <= '1';
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while empty = '0' loop
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assert unsigned(dataOut) = dataOffset + readIndex
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report "FIFO readback error"
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severity error;
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readIndex := readIndex + 1;
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wait until rising_edge(clock_int);
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end loop;
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read_int <= '0';
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--..........................................................................
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-- end of tests
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wait for testInterval;
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assert false
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report "END SIMULATION"
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severity failure;
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wait;
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end process;
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dataIn <= std_ulogic_vector(to_signed(dataIn_int, dataIn'length));
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read <= read_int;
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dataValid <= '1' when (read_int = '1') and (empty = '0')
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else '0';
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dataRead <= to_integer(signed(dataOut)) when dataValid = '1'
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else 0;
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END ARCHITECTURE test;
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