137 lines
7.6 KiB
VHDL
137 lines
7.6 KiB
VHDL
|
-- #################################################################################################
|
||
|
|
-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> #
|
||
|
|
-- # ********************************************************************************************* #
|
||
|
|
-- # This version is intended for SIMULATION ONLY! #
|
||
|
|
-- # It implements the IMEM as pre-initialized RAM. #
|
||
|
|
-- # ********************************************************************************************* #
|
||
|
|
-- # BSD 3-Clause License #
|
||
|
|
-- # #
|
||
|
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||
|
|
-- # #
|
||
|
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||
|
|
-- # permitted provided that the following conditions are met: #
|
||
|
|
-- # #
|
||
|
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||
|
|
-- # conditions and the following disclaimer. #
|
||
|
|
-- # #
|
||
|
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||
|
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||
|
|
-- # provided with the distribution. #
|
||
|
|
-- # #
|
||
|
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||
|
|
-- # endorse or promote products derived from this software without specific prior written #
|
||
|
|
-- # permission. #
|
||
|
|
-- # #
|
||
|
|
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||
|
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||
|
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||
|
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||
|
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||
|
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||
|
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||
|
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||
|
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||
|
|
-- # ********************************************************************************************* #
|
||
|
|
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||
|
|
-- #################################################################################################
|
||
|
|
|
||
|
|
library ieee;
|
||
|
|
use ieee.std_logic_1164.all;
|
||
|
|
use ieee.numeric_std.all;
|
||
|
|
|
||
|
|
library neorv32;
|
||
|
|
use neorv32.neorv32_package.all;
|
||
|
|
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
|
||
|
|
|
||
|
|
architecture neorv32_imem_rtl of neorv32_imem is
|
||
|
|
|
||
|
|
-- IO space: module base address --
|
||
|
|
constant hi_abb_c : natural := 31; -- high address boundary bit
|
||
|
|
constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit
|
||
|
|
|
||
|
|
-- local signals --
|
||
|
|
signal acc_en : std_ulogic;
|
||
|
|
signal rdata : std_ulogic_vector(31 downto 0);
|
||
|
|
signal rden : std_ulogic;
|
||
|
|
signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
|
||
|
|
|
||
|
|
-- ---------------------------------------------------- --
|
||
|
|
-- << SIMULATION ONLY!!! >> IMEM as pre-initialized RAM --
|
||
|
|
-- ---------------------------------------------------- --
|
||
|
|
|
||
|
|
-- application (image) size in bytes --
|
||
|
|
constant imem_app_size_c : natural := (application_init_image'length)*4;
|
||
|
|
|
||
|
|
-- RAM - initialized with executable code --
|
||
|
|
signal mem_ram : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
|
||
|
|
|
||
|
|
-- read data --
|
||
|
|
signal mem_ram_rd : std_ulogic_vector(31 downto 0);
|
||
|
|
|
||
|
|
begin
|
||
|
|
|
||
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal [SIM-only!] IMEM as RAM (" & natural'image(IMEM_SIZE) &
|
||
|
|
" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;
|
||
|
|
--
|
||
|
|
assert not (imem_app_size_c > IMEM_SIZE) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) &
|
||
|
|
" bytes) does not fit into processor-internal IMEM (" & natural'image(IMEM_SIZE) & " bytes)!" severity error;
|
||
|
|
|
||
|
|
|
||
|
|
-- Access Control -------------------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
|
||
|
|
addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned
|
||
|
|
|
||
|
|
|
||
|
|
-- Implement IMEM as pre-initialized RAM --------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
mem_access: process(clk_i)
|
||
|
|
begin
|
||
|
|
if rising_edge(clk_i) then
|
||
|
|
if (acc_en = '1') then
|
||
|
|
if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0
|
||
|
|
mem_ram(to_integer(unsigned(addr)))(07 downto 00) <= data_i(07 downto 00);
|
||
|
|
else
|
||
|
|
mem_ram_rd(07 downto 00) <= mem_ram(to_integer(unsigned(addr)))(07 downto 00);
|
||
|
|
end if;
|
||
|
|
if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1
|
||
|
|
mem_ram(to_integer(unsigned(addr)))(15 downto 08) <= data_i(15 downto 08);
|
||
|
|
else
|
||
|
|
mem_ram_rd(15 downto 08) <= mem_ram(to_integer(unsigned(addr)))(15 downto 08);
|
||
|
|
end if;
|
||
|
|
if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2
|
||
|
|
mem_ram(to_integer(unsigned(addr)))(23 downto 16) <= data_i(23 downto 16);
|
||
|
|
else
|
||
|
|
mem_ram_rd(23 downto 16) <= mem_ram(to_integer(unsigned(addr)))(23 downto 16);
|
||
|
|
end if;
|
||
|
|
if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3
|
||
|
|
mem_ram(to_integer(unsigned(addr)))(31 downto 24) <= data_i(31 downto 24);
|
||
|
|
else
|
||
|
|
mem_ram_rd(31 downto 24) <= mem_ram(to_integer(unsigned(addr)))(31 downto 24);
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end if;
|
||
|
|
end process mem_access;
|
||
|
|
|
||
|
|
-- read data --
|
||
|
|
rdata <= mem_ram_rd;
|
||
|
|
|
||
|
|
|
||
|
|
-- Bus Feedback ---------------------------------------------------------------------------
|
||
|
|
-- -------------------------------------------------------------------------------------------
|
||
|
|
bus_feedback: process(clk_i)
|
||
|
|
begin
|
||
|
|
if rising_edge(clk_i) then
|
||
|
|
rden <= acc_en and rden_i;
|
||
|
|
ack_o <= acc_en and (rden_i or wren_i);
|
||
|
|
end if;
|
||
|
|
end process bus_feedback;
|
||
|
|
|
||
|
|
-- output gate --
|
||
|
|
data_o <= rdata when (rden = '1') else (others => '0');
|
||
|
|
|
||
|
|
|
||
|
|
end neorv32_imem_rtl;
|