33 lines
839 B
VHDL
33 lines
839 B
VHDL
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ARCHITECTURE rtl OF dataMemory IS
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-- Bank of data
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type t_dataBank is array (0 to (2**g_memoryNbBits)-1) of
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std_ulogic_vector(g_dataWidth-1 downto 0);
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-- A bank of data
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signal larr_data: t_dataBank;
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BEGIN
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process(rst, clk)
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begin
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if rst = '1' then
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larr_data <= (others => (others => '0')) after g_tMemWr;
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elsif rising_edge(clk) then
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if en = '1' and writeEn = '1' then
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-- skip the two last bits (since we do only +4)
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larr_data(to_integer(unsigned(
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address(g_memoryNbBits+1 downto 2)
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))) <= writeData after (g_tMemWr + g_tSetup);
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end if;
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end if;
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end process;
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-- Comb. read
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-- skip the two last bits (since we do only +4)
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readData <= larr_data(to_integer(unsigned(
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address(g_memoryNbBits+1 downto 2)
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))) after g_tMemRd;
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END ARCHITECTURE rtl;
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