17 lines
296 B
VHDL
17 lines
296 B
VHDL
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ARCHITECTURE rtl OF bufferUnsignedEnable IS
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BEGIN
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buffering:process(rst, CLK)
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begin
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if rst = '1' then
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out1 <= (others=>'0') after g_tPC;
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elsif rising_edge(CLK) then
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if EN = '1' then
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out1 <= in1 after g_tPC;
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end if;
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end if;
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end process buffering;
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END ARCHITECTURE rtl;
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