27 lines
983 B
VHDL
27 lines
983 B
VHDL
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ARCHITECTURE rtl OF extend IS
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BEGIN
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extend : process(input, src)
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begin
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case src is
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when "00" => -- I-type
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extended <= (12 to 31 => input(31)) &
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input(31 downto 20) after g_tExt;
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when "01" => -- S-types (stores)
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extended <= (12 to 31 => input(31)) &
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input(31 downto 25) & input(11 downto 7) after g_tExt;
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when "10" => -- B-type (branches)
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extended <= (12 to 31 => input(31)) & input(7) &
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input(30 downto 25) & input(11 downto 8) & '0' after g_tExt;
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when "11" => -- J-type (jal)
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extended <= (20 to 31 => input(31)) &
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input(19 downto 12) & input(20) &
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input(30 downto 21) & '0' after g_tExt;
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when others => -- impossible
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extended <= (others => '-') after g_tExt;
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end case;
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end process extend;
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END ARCHITECTURE rtl;
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