76 lines
2.5 KiB
VHDL
76 lines
2.5 KiB
VHDL
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library ieee ;
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use ieee.std_logic_1164.all;
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package components is
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-- Yosys wrapper components
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component EHXPLLL
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generic
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(
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CLKI_DIV : integer := 1;
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CLKFB_DIV : integer := 1;
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CLKOP_DIV : integer := 8;
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CLKOS_DIV : integer := 8;
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CLKOS2_DIV : integer := 8;
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CLKOS3_DIV : integer := 8;
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CLKOP_ENABLE : string := "ENABLED";
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CLKOS_ENABLE : string := "DISABLED";
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CLKOS2_ENABLE : string := "DISABLED";
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CLKOS3_ENABLE : string := "DISABLED";
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CLKOP_CPHASE : integer := 0;
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CLKOS_CPHASE : integer := 0;
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CLKOS2_CPHASE : integer := 0;
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CLKOS3_CPHASE : integer := 0;
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CLKOP_FPHASE : integer := 0;
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CLKOS_FPHASE : integer := 0;
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CLKOS2_FPHASE : integer := 0;
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CLKOS3_FPHASE : integer := 0;
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FEEDBK_PATH : string := "CLKOP";
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CLKOP_TRIM_POL : string := "RISING";
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CLKOP_TRIM_DELAY : integer := 0;
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CLKOS_TRIM_POL : string := "RISING";
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CLKOS_TRIM_DELAY : integer := 0;
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OUTDIVIDER_MUXA : string := "DIVA";
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OUTDIVIDER_MUXB : string := "DIVB";
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OUTDIVIDER_MUXC : string := "DIVC";
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OUTDIVIDER_MUXD : string := "DIVD";
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PLL_LOCK_MODE : integer := 0;
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PLL_LOCK_DELAY : integer := 200;
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STDBY_ENABLE : string := "DISABLED";
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REFIN_RESET : string := "DISABLED";
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SYNC_ENABLE : string := "DISABLED";
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INT_LOCK_STICKY : string := "ENABLED";
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DPHASE_SOURCE : string := "DISABLED";
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PLLRST_ENA : string := "DISABLED";
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INTFB_WAKE : string := "DISABLED"
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);
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port
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(
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CLKI : IN std_logic := 'X';
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CLKFB : IN std_logic := 'X';
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RST : IN std_logic := 'X';
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STDBY : IN std_logic := 'X';
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PLLWAKESYNC : IN std_logic := 'X';
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PHASESEL1 : IN std_logic := 'X';
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PHASESEL0 : IN std_logic := 'X';
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PHASEDIR : IN std_logic := 'X';
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PHASESTEP : IN std_logic := 'X';
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PHASELOADREG : IN std_logic := 'X';
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ENCLKOP : IN std_logic := 'X';
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ENCLKOS : IN std_logic := 'X';
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ENCLKOS2 : IN std_logic := 'X';
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ENCLKOS3 : IN std_logic := 'X';
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CLKOP : OUT std_logic := 'X';
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CLKOS : OUT std_logic := 'X';
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CLKOS2 : OUT std_logic := 'X';
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CLKOS3 : OUT std_logic := 'X';
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LOCK : OUT std_logic := 'X';
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INTLOCK : OUT std_logic := 'X';
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REFCLK : OUT std_logic := 'X';
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CLKINTFB : OUT std_logic := 'X'
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);
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end component;
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end package;
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