75 lines
2.7 KiB
Makefile
75 lines
2.7 KiB
Makefile
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ifndef NEORV32_ROOT
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$(error NEORV32_ROOT is undefined)
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endif
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NEORV32_LOCAL_RTL ?= $(NEORV32_ROOT)/sim/work
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TARGET_SIM ?= ghdl
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TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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NEORV32_MARCH ?= rv32i
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NEORV32_MABI ?= ilp32
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
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RISCV_READELF ?= $(RISCV_PREFIX)readelf
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RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=$(NEORV32_MARCH) -mabi=$(NEORV32_MABI)
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NEORV32_LINK ?= link.imem_rom.ld
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COMPILE_TARGET ?= \
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$$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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$$(RISCV_TARGET_FLAGS) \
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-I$(ROOTDIR)/riscv-test-suite/env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/$(NEORV32_LINK) \
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$$(<) -o $$@
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NEORV32_CPU_EXTENSION_RISCV_C ?= false
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NEORV32_CPU_EXTENSION_RISCV_E ?= false
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NEORV32_CPU_EXTENSION_RISCV_M ?= false
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NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= false
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NEORV32_MEM_INT_IMEM_SIZE ?= '2097152'
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NEORV32_SOFTWARE_EXAMPLE ?= $(NEORV32_ROOT)/sw/example/blink_led
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ifeq ($(NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI), true)
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RUN_TARGET ?= \
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echo "copying/using SIM-only IMEM (pre-initialized RAM!)"; \
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rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
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cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.iram.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
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else
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RUN_TARGET ?= \
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echo "copying/using SIM-only IMEM (pre-initialized ROM!)"; \
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rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \
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cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd;
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endif
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RUN_TARGET += \
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cd $(work_dir_isa); \
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echo ">"; \
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rm -f $(NEORV32_ROOT)/sim/*.out; \
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make -C $(NEORV32_SOFTWARE_EXAMPLE) main.elf; \
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cp -f $< $(NEORV32_SOFTWARE_EXAMPLE)/main.elf; \
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make -C $(NEORV32_SOFTWARE_EXAMPLE) main.bin install; \
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touch $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out; \
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GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_ROOT)/sim/simple/ghdl.run.sh \
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--stop-time=$(SIM_TIME) \
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-gCPU_EXTENSION_RISCV_A=false \
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-gCPU_EXTENSION_RISCV_C=$(NEORV32_CPU_EXTENSION_RISCV_C) \
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-gCPU_EXTENSION_RISCV_E=$(NEORV32_CPU_EXTENSION_RISCV_E) \
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-gCPU_EXTENSION_RISCV_M=$(NEORV32_CPU_EXTENSION_RISCV_M) \
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-gCPU_EXTENSION_RISCV_U=false \
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-gCPU_EXTENSION_RISCV_Zicsr=true \
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-gCPU_EXTENSION_RISCV_Zifencei=true \
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-gEXT_IMEM_C=false \
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-gMEM_INT_IMEM_SIZE=$(NEORV32_MEM_INT_IMEM_SIZE); \
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cp $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out $(*).signature.output; \
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echo "<";
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