39 lines
1.3 KiB
VHDL
39 lines
1.3 KiB
VHDL
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library ieee;
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use ieee.math_real.all;
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ARCHITECTURE test OF DAC_tester IS
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal sClock: std_uLogic := '1';
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signal sineFrequency: real := 20.0E3;
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signal tReal: real := 0.0;
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signal outAmplitude: real := 1.0;
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signal outReal: real := 0.0;
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signal outUnsigned: unsigned(parallelIn'range);
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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reset <= '1', '0' after 2*clockPeriod;
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------------------------------------------------------------------------------
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-- time signals
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process(sClock)
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begin
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if rising_edge(sClock) then
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tReal <= tReal + 1.0/clockFrequency;
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end if;
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end process;
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outReal <= outAmplitude * ( sin(2.0*math_pi*sineFrequency*tReal) + 1.0) / 2.0;
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outUnsigned <= to_unsigned(integer(outReal * real(2**(outUnsigned'length)-1)), outUnsigned'length);
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parallelIn <= outUnsigned;
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-- parallelIn <= shift_left(to_unsigned(1, parallelIn'length), parallelIn'length-1);
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-- parallelIn <= shift_left(to_unsigned(3, parallelIn'length), parallelIn'length-2);
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END ARCHITECTURE test;
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