27 lines
648 B
VHDL
27 lines
648 B
VHDL
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ARCHITECTURE rtl OF instructionForwarder IS
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signal lvec_irMem : std_ulogic_vector(readData'range);
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BEGIN
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-- forwardIR : process(rst, clk)
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-- begin
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-- if rst = '1' then
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-- lvec_irMem <= (others => '0');
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-- elsif rising_edge(clk) then
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-- if en = '1' and IRWrite = '1' then
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-- lvec_irMem <= readData;
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-- end if;
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-- end if;
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-- end process forwardIR;
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forwardIR : process(readData, irWrite)
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begin
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if irWrite = '1' then
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lvec_irMem <= readData;
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end if;
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end process forwardIR;
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instruction <= lvec_irMem;
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END ARCHITECTURE rtl;
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