75 lines
2.4 KiB
VHDL
75 lines
2.4 KiB
VHDL
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LIBRARY std;
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USE std.TEXTIO.all;
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE RTL OF uvmAhbDriver IS
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constant flipflopDelay: time := 1 ns;
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signal hAddr1, hWData1, hWData2: natural := 0;
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signal hWrite1, hWrite2, hRead1, hRead2: std_ulogic := '0';
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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hReset_n <= not(reset);
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hClk <= clock;
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------------------------------------------------------------------------------
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-- interpret transaction
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interpretTransaction: process(driverTransaction)
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variable my_line : line;
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variable command_part : line;
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begin
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write(my_line, driverTransaction);
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read_first(my_line, command_part);
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if command_part.all = "write" then
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read_first(my_line, command_part);
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hAddr1 <= sscanf(command_part.all);
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read_first(my_line, command_part);
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hWData1 <= sscanf(command_part.all);
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hWrite1 <= '1', '0' after 1 ns;
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elsif command_part.all = "read" then
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read_first(my_line, command_part);
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hAddr1 <= sscanf(command_part.all);
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hRead1 <= '1', '0' after 1 ns;
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end if;
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deallocate(my_line);
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end process interpretTransaction;
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-- expand pulses to the next clock
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expandReadWrite: process
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begin
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hRead2 <= '0';
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hWrite2 <= '0';
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wait on hRead1, hWrite1;
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hRead2 <= hRead1;
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hWrite2 <= hWrite1;
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wait until rising_edge(clock);
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end process expandReadWrite;
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-- delay signals 1 or 2 clock periods
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synchAccess: process(reset, clock)
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begin
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if reset = '1' then
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hAddr <= (others => '0');
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hWData2 <= 0;
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hWData <= (others => '0');
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hWrite <= '0';
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hSel <= '0';
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hTrans <= transIdle;
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elsif rising_edge(clock) then
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hAddr <= to_unsigned(hAddr1, hAddr'length) after flipflopDelay;
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hWData2 <= hWData1;
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hWData <= std_ulogic_vector(to_unsigned(hWData2, hWData'length)) after flipflopDelay;
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hWrite <= hWrite2 after flipflopDelay;
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hSel <= hWrite2 or hRead2 after flipflopDelay;
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if (hWrite2 = '1') or (hRead2 = '1') then
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hTrans <= transNonSeq after flipflopDelay;
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else
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hTrans <= transIdle after flipflopDelay;
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end if;
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end if;
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end process synchAccess;
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END ARCHITECTURE RTL;
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