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SEm-Labos/Libs/NanoBlaze/hds/controller/symbol.sb

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(vvPair
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(vvPair
variable "day"
value "jeu."
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(vvPair
variable "dd"
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variable "entity_name"
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variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/Labs/ElN/NanoBlaze/NanoBlaze/work"
)
(vvPair
variable "mm"
value "09"
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(vvPair
variable "module_name"
value "controller"
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(vvPair
variable "month"
value "sept."
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variable "month_long"
value "septembre"
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(vvPair
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value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb"
)
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)
(vvPair
variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
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value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
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(vvPair
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value "<TBD>"
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value "<TBD>"
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(vvPair
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(vvPair
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value "controller"
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(vvPair
variable "user"
value "cof"
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(vvPair
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value "2009.2 (Build 10)"
)
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value "symbol"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "45250,120625,46000,121375"
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tg (CPTG
uid 78,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "47000,120500,48200,121500"
st "en"
blo "47000,121300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,14200,21000,15000"
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t "std_ulogic"
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uid 81,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "62000,31625,62750,32375"
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tg (CPTG
uid 83,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "58500,31500,61000,32500"
st "incPC"
ju 2
blo "61000,32300"
tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
font "Courier New,8,0"
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xt "0,20600,21000,21400"
st "incPC : OUT std_ulogic ;
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thePort (LogicalPort
m 1
decl (Decl
n "incPC"
t "std_ulogic"
o 12
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uid 86,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "62000,85625,62750,86375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "56000,85500,61000,86500"
st "instrDataSel"
ju 2
blo "61000,86300"
tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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xt "0,21400,21000,22200"
st "instrDataSel : OUT std_ulogic ;
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thePort (LogicalPort
m 1
decl (Decl
n "instrDataSel"
t "std_ulogic"
o 13
suid 8,0
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uid 91,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "45250,9625,46000,10375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "47000,9500,48200,10500"
st "int"
blo "47000,10300"
tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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xt "0,15000,21000,15800"
st "int : IN std_uLogic ;
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thePort (LogicalPort
decl (Decl
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t "std_uLogic"
o 5
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "45250,11625,46000,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "47000,11500,49400,12500"
st "intAck"
blo "47000,12300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,22200,21000,23000"
st "intAck : OUT std_ulogic ;
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thePort (LogicalPort
m 1
decl (Decl
n "intAck"
t "std_ulogic"
o 14
suid 10,0
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uid 101,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "62000,55625,62750,56375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "58000,55500,61000,56500"
st "intCode"
ju 2
blo "61000,56300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,15800,38500,16600"
st "intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ) ;
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)
thePort (LogicalPort
decl (Decl
n "intCode"
t "std_ulogic_vector"
b "( intCodeBitNb-1 DOWNTO 0 )"
o 6
suid 11,0
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uid 106,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "62000,33625,62750,34375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "54500,33500,61000,34500"
st "loadInstrAddress"
ju 2
blo "61000,34300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,23000,21000,23800"
st "loadInstrAddress : OUT std_ulogic ;
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thePort (LogicalPort
m 1
decl (Decl
n "loadInstrAddress"
t "std_ulogic"
o 15
suid 12,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "62000,35625,62750,36375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "55500,35500,61000,36500"
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ju 2
blo "61000,36300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,23800,21000,24600"
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decl (Decl
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
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xt "62000,61625,62750,62375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "58000,61500,61000,62500"
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blo "61000,62300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,16600,37000,17400"
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decl (Decl
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b "(opCodeBitNb-1 DOWNTO 0)"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "62000,87625,62750,88375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "57600,87500,61000,88500"
st "portInSel"
ju 2
blo "61000,88300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,24600,21000,25400"
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thePort (LogicalPort
m 1
decl (Decl
n "portInSel"
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o 17
suid 15,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "62000,73625,62750,74375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "56500,73500,61000,74500"
st "readStrobe"
ju 2
blo "61000,74300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,26200,21000,27000"
st "readStrobe : OUT std_uLogic ;
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thePort (LogicalPort
m 1
decl (Decl
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o 18
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "62000,83625,62750,84375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "55100,83500,61000,84500"
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blo "61000,84300"
tm "CptPortNameMgr"
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decl (Decl
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "45250,124625,46000,125375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "47000,124500,49100,125500"
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blo "47000,125300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,17400,21000,18200"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "62000,89625,62750,90375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "55400,89500,61000,90500"
st "scratchpadSel"
ju 2
blo "61000,90300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,28600,21000,29400"
st "scratchpadSel : OUT std_ulogic ;
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m 1
decl (Decl
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "62000,119625,62750,120375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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blo "61000,120300"
tm "CptPortNameMgr"
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xt "0,29400,21000,30200"
st "scratchpadWrite : OUT std_ulogic ;
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decl (Decl
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ps "OnEdgeStrategy"
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "62000,11625,62750,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "57800,11500,61000,12500"
st "storePC"
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blo "61000,12300"
tm "CptPortNameMgr"
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va (VaSet
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xt "0,30200,21000,31000"
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decl (Decl
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ps "OnEdgeStrategy"
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ro 90
va (VaSet
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xt "62000,75625,62750,76375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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xt "56400,75500,61000,76500"
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blo "61000,76300"
tm "CptPortNameMgr"
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ps "OnEdgeStrategy"
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ro 270
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blo "61000,100300"
tm "CptPortNameMgr"
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xt "0,19000,21000,19800"
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ps "OnEdgeStrategy"
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ro 90
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blo "61000,92300"
tm "CptPortNameMgr"
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decl (Decl
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ro 270
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blo "61000,64300"
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