SEm-Labos/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer/struct.bd

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)
*32 (Net
uid 16811,0
decl (Decl
n "hReady"
t "std_ulogic"
o 11
suid 90,0
)
declText (MLText
uid 16812,0
va (VaSet
)
xt "2000,10000,16400,11200"
st "hReady         : std_ulogic"
)
)
*33 (Net
uid 16825,0
decl (Decl
n "hResp"
t "std_ulogic"
o 12
suid 91,0
)
declText (MLText
uid 16826,0
va (VaSet
)
xt "2000,11200,16100,12400"
st "hResp          : std_ulogic"
)
)
*34 (PortIoIn
uid 16933,0
shape (CompositeShape
uid 16934,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16935,0
sl 0
ro 270
xt "36000,18625,37500,19375"
)
(Line
uid 16936,0
sl 0
ro 270
xt "37500,19000,38000,19000"
pts [
"37500,19000"
"38000,19000"
]
)
]
)
tg (WTG
uid 16937,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16938,0
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "31800,18500,35000,20000"
st "hClk"
ju 2
blo "35000,19700"
tm "WireNameMgr"
)
)
)
*35 (Net
uid 16945,0
decl (Decl
n "hClk"
t "std_ulogic"
o 13
suid 92,0
)
declText (MLText
uid 16946,0
va (VaSet
)
xt "2000,12400,15600,13600"
st "hClk           : std_ulogic"
)
)
*36 (PortIoIn
uid 16947,0
shape (CompositeShape
uid 16948,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16949,0
sl 0
ro 270
xt "36000,20625,37500,21375"
)
(Line
uid 16950,0
sl 0
ro 270
xt "37500,21000,38000,21000"
pts [
"37500,21000"
"38000,21000"
]
)
]
)
tg (WTG
uid 16951,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16952,0
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "28900,20500,35000,22000"
st "hReset_n"
ju 2
blo "35000,21700"
tm "WireNameMgr"
)
)
)
*37 (Net
uid 16959,0
decl (Decl
n "hReset_n"
t "std_ulogic"
o 14
suid 93,0
)
declText (MLText
uid 16960,0
va (VaSet
)
xt "2000,13600,16800,14800"
st "hReset_n       : std_ulogic"
)
)
*38 (PortIoOut
uid 17020,0
shape (CompositeShape
uid 17021,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 17022,0
sl 0
ro 90
xt "36000,14625,37500,15375"
)
(Line
uid 17023,0
sl 0
ro 90
xt "37500,15000,38000,15000"
pts [
"38000,15000"
"37500,15000"
]
)
]
)
tg (WTG
uid 17024,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17025,0
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "30600,14300,35000,15800"
st "hResp"
ju 2
blo "35000,15500"
tm "WireNameMgr"
)
)
)
*39 (PortIoOut
uid 17026,0
shape (CompositeShape
uid 17027,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 17028,0
sl 0
ro 90
xt "36000,12625,37500,13375"
)
(Line
uid 17029,0
sl 0
ro 90
xt "37500,13000,38000,13000"
pts [
"38000,13000"
"37500,13000"
]
)
]
)
tg (WTG
uid 17030,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17031,0
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "30100,12300,35000,13800"
st "hReady"
ju 2
blo "35000,13500"
tm "WireNameMgr"
)
)
)
*40 (HdlText
uid 17109,0
optionalChildren [
*41 (EmbeddedText
uid 17114,0
commentText (CommentText
uid 17115,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 17116,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "66000,24000,74000,26000"
)
oxt "0,0,18000,5000"
text (MLText
uid 17117,0
va (VaSet
)
xt "66200,24200,74100,25400"
st "
reset <= not hReset_n;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 8000
)
)
)
]
shape (Rectangle
uid 17110,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "66000,23000,74000,27000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 17111,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*42 (Text
uid 17112,0
va (VaSet
)
xt "66400,27000,68000,28000"
st "eb3"
blo "66400,27800"
tm "HdlTextNameMgr"
)
*43 (Text
uid 17113,0
va (VaSet
)
xt "66400,28000,67200,29000"
st "3"
blo "66400,28800"
tm "HdlTextNumberMgr"
)
]
)
)
*44 (SaComponent
uid 17506,0
optionalChildren [
*45 (CptPort
uid 17438,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17439,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,18625,46000,19375"
)
tg (CPTG
uid 17440,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17441,0
va (VaSet
font "Arial,9,0"
)
xt "47000,18400,49400,19600"
st "hClk"
blo "47000,19300"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_ulogic"
o 8
suid 1,0
)
)
)
*46 (CptPort
uid 17442,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17443,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,625,46000,1375"
)
tg (CPTG
uid 17444,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17445,0
va (VaSet
font "Arial,9,0"
)
xt "47000,400,49900,1600"
st "hAddr"
blo "47000,1300"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 downto 0)"
o 10
suid 2,0
)
)
)
*47 (CptPort
uid 17446,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17447,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,10625,46000,11375"
)
tg (CPTG
uid 17448,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17449,0
va (VaSet
font "Arial,9,0"
)
xt "47000,10400,50700,11600"
st "hRData"
blo "47000,11300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 9
suid 11,0
)
)
)
*48 (CptPort
uid 17450,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17451,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53625,-3750,54375,-3000"
)
tg (CPTG
uid 17452,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17453,0
va (VaSet
font "Arial,9,0"
)
xt "52000,-2000,55600,-800"
st "testOut"
blo "52000,-1100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 1
suid 12,0
)
)
)
*49 (CptPort
uid 17454,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17455,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,625,62750,1375"
)
tg (CPTG
uid 17456,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17457,0
va (VaSet
font "Arial,9,0"
)
xt "59200,400,61000,1600"
st "run"
ju 2
blo "61000,1300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 4
suid 2014,0
)
)
)
*50 (CptPort
uid 17458,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17459,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,4625,62750,5375"
)
tg (CPTG
uid 17460,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17461,0
va (VaSet
font "Arial,9,0"
)
xt "54600,4400,61000,5600"
st "updatePeriod"
ju 2
blo "61000,5300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 5
suid 2015,0
)
)
)
*51 (CptPort
uid 17462,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17463,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,8625,62750,9375"
)
tg (CPTG
uid 17464,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17465,0
va (VaSet
font "Arial,9,0"
)
xt "57900,8400,61000,9600"
st "memX"
ju 2
blo "61000,9300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 2
suid 2016,0
)
)
)
*52 (CptPort
uid 17466,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17467,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,10625,62750,11375"
)
tg (CPTG
uid 17468,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17469,0
va (VaSet
font "Arial,9,0"
)
xt "57700,10400,61000,11600"
st "memY"
ju 2
blo "61000,11300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 3
suid 2017,0
)
)
)
*53 (CptPort
uid 17470,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17471,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,2625,62750,3375"
)
tg (CPTG
uid 17472,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17473,0
va (VaSet
font "Arial,9,0"
)
xt "54500,2400,61000,3600"
st "interpolateLin"
ju 2
blo "61000,3300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 6
suid 2018,0
)
)
)
*54 (CptPort
uid 17474,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17475,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,20625,46000,21375"
)
tg (CPTG
uid 17476,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17477,0
va (VaSet
font "Arial,9,0"
)
xt "47000,20400,51500,21600"
st "hReset_n"
blo "47000,21300"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_ulogic"
o 11
suid 2021,0
)
)
)
*55 (CptPort
uid 17478,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17479,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,6625,62750,7375"
)
tg (CPTG
uid 17480,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17481,0
va (VaSet
font "Arial,9,0"
)
xt "54700,6400,61000,7600"
st "newPolynom"
ju 2
blo "61000,7300"
)
)
thePort (LogicalPort
decl (Decl
n "newPolynom"
t "std_ulogic"
o 7
suid 2022,0
)
)
)
*56 (CptPort
uid 17482,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17483,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,2625,46000,3375"
)
tg (CPTG
uid 17484,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17485,0
va (VaSet
font "Arial,9,0"
)
xt "47000,2400,50900,3600"
st "hWData"
blo "47000,3300"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 12
suid 2023,0
)
)
)
*57 (CptPort
uid 17486,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17487,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,4625,46000,5375"
)
tg (CPTG
uid 17488,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17489,0
va (VaSet
font "Arial,9,0"
)
xt "47000,4400,50300,5600"
st "hTrans"
blo "47000,5300"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 downto 0)"
o 13
suid 2024,0
)
)
)
*58 (CptPort
uid 17490,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17491,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,6625,46000,7375"
)
tg (CPTG
uid 17492,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17493,0
va (VaSet
font "Arial,9,0"
)
xt "47000,6400,50200,7600"
st "hWrite"
blo "47000,7300"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_ulogic"
o 14
suid 2025,0
)
)
)
*59 (CptPort
uid 17494,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17495,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,8625,46000,9375"
)
tg (CPTG
uid 17496,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17497,0
va (VaSet
font "Arial,9,0"
)
xt "47000,8400,49300,9600"
st "hSel"
blo "47000,9300"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_ulogic"
o 15
suid 2026,0
)
)
)
*60 (CptPort
uid 17498,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17499,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,12625,46000,13375"
)
tg (CPTG
uid 17500,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17501,0
va (VaSet
font "Arial,9,0"
)
xt "47000,12400,50800,13600"
st "hReady"
blo "47000,13300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_ulogic"
o 16
suid 2027,0
)
)
)
*61 (CptPort
uid 17502,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17503,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,14625,46000,15375"
)
tg (CPTG
uid 17504,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17505,0
va (VaSet
font "Arial,9,0"
)
xt "47000,14400,50200,15600"
st "hResp"
blo "47000,15300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_ulogic"
o 17
suid 2028,0
)
)
)
]
shape (Rectangle
uid 17507,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "46000,-3000,62000,23000"
)
oxt "44000,4000,60000,30000"
ttg (MlTextGroup
uid 17508,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*62 (Text
uid 17509,0
va (VaSet
font "Arial,9,1"
)
xt "46600,22800,54300,23900"
st "SystemOnChip"
blo "46600,23700"
tm "BdLibraryNameMgr"
)
*63 (Text
uid 17510,0
va (VaSet
font "Arial,9,1"
)
xt "46600,23700,57000,24800"
st "ahbBeamerRegisters"
blo "46600,24600"
tm "CptNameMgr"
)
*64 (Text
uid 17511,0
va (VaSet
font "Arial,9,1"
)
xt "46600,24600,49900,25700"
st "I_regs"
blo "46600,25500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17512,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17513,0
text (MLText
uid 17514,0
va (VaSet
)
xt "46000,26600,78500,31400"
st "updatePeriodBitNb   = updatePeriodBitNb      ( positive )  
signalBitNb         = signalBitNb            ( positive )  
patternAddressBitNb = patternAddressBitNb    ( positive )  
testOutBitNb        = testOutBitNb           ( positive )  "
)
header ""
)
elements [
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*65 (SaComponent
uid 17559,0
optionalChildren [
*66 (CptPort
uid 17515,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17516,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,14625,78000,15375"
)
tg (CPTG
uid 17517,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17518,0
va (VaSet
font "Arial,9,0"
)
xt "79000,14400,81700,15600"
st "clock"
blo "79000,15300"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 1,0
)
)
)
*67 (CptPort
uid 17519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,625,78000,1375"
)
tg (CPTG
uid 17521,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17522,0
va (VaSet
font "Arial,9,0"
)
xt "79000,400,80800,1600"
st "run"
blo "79000,1300"
)
)
thePort (LogicalPort
decl (Decl
n "run"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*68 (CptPort
uid 17523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,625,94750,1375"
)
tg (CPTG
uid 17525,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17526,0
va (VaSet
font "Arial,9,0"
)
xt "90701,400,93001,1600"
st "outX"
ju 2
blo "93001,1300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 1
suid 3,0
)
)
)
*69 (CptPort
uid 17527,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17528,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,16625,78000,17375"
)
tg (CPTG
uid 17529,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17530,0
va (VaSet
font "Arial,9,0"
)
xt "79000,16400,81600,17600"
st "reset"
blo "79000,17300"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*70 (CptPort
uid 17531,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17532,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,2625,94750,3375"
)
tg (CPTG
uid 17533,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17534,0
va (VaSet
font "Arial,9,0"
)
xt "90501,2400,93001,3600"
st "outY"
ju 2
blo "93001,3300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*71 (CptPort
uid 17535,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17536,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,6625,94750,7375"
)
tg (CPTG
uid 17537,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17538,0
va (VaSet
font "Arial,9,0"
)
xt "88301,6400,93001,7600"
st "selSinCos"
ju 2
blo "93001,7300"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 6
suid 13,0
)
)
)
*72 (CptPort
uid 17539,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17540,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,2625,78000,3375"
)
tg (CPTG
uid 17541,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17542,0
va (VaSet
font "Arial,9,0"
)
xt "79000,2400,85500,3600"
st "interpolateLin"
blo "79000,3300"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 7
suid 2014,0
)
)
)
*73 (CptPort
uid 17543,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17544,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,4625,78000,5375"
)
tg (CPTG
uid 17545,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17546,0
va (VaSet
font "Arial,9,0"
)
xt "79000,4400,85400,5600"
st "updatePeriod"
blo "79000,5300"
)
)
thePort (LogicalPort
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 8
suid 2015,0
)
)
)
*74 (CptPort
uid 17547,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17548,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,8625,78000,9375"
)
tg (CPTG
uid 17549,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17550,0
va (VaSet
font "Arial,9,0"
)
xt "79000,8400,82100,9600"
st "memX"
blo "79000,9300"
)
)
thePort (LogicalPort
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 2016,0
)
)
)
*75 (CptPort
uid 17551,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17552,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,10625,78000,11375"
)
tg (CPTG
uid 17553,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17554,0
va (VaSet
font "Arial,9,0"
)
xt "79000,10400,82300,11600"
st "memY"
blo "79000,11300"
)
)
thePort (LogicalPort
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 10
suid 2018,0
)
)
)
*76 (CptPort
uid 17555,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17556,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,6625,78000,7375"
)
tg (CPTG
uid 17557,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17558,0
va (VaSet
font "Arial,9,0"
)
xt "79000,6400,85300,7600"
st "newPolynom"
blo "79000,7300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "newPolynom"
t "std_ulogic"
o 11
suid 2019,0
)
)
)
]
shape (Rectangle
uid 17560,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,-3000,94000,19000"
)
oxt "42000,9000,58000,31000"
ttg (MlTextGroup
uid 17561,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*77 (Text
uid 17562,0
va (VaSet
font "Arial,9,1"
)
xt "78600,18800,86300,19900"
st "SystemOnChip"
blo "78600,19700"
tm "BdLibraryNameMgr"
)
*78 (Text
uid 17563,0
va (VaSet
font "Arial,9,1"
)
xt "78600,19700,88700,20800"
st "ahbBeamerOperator"
blo "78600,20600"
tm "CptNameMgr"
)
*79 (Text
uid 17564,0
va (VaSet
font "Arial,9,1"
)
xt "78600,20600,81100,21700"
st "I_op"
blo "78600,21500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17565,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17566,0
text (MLText
uid 17567,0
va (VaSet
)
xt "78000,22600,108100,25000"
st "updatePeriodBitNb = updatePeriodBitNb    ( positive )  
signalBitNb       = signalBitNb          ( positive )  "
)
header ""
)
elements [
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*80 (Wire
uid 115,0
shape (OrthoPolyLine
uid 116,0
va (VaSet
vasetType 3
)
xt "94750,1000,102000,1000"
pts [
"94750,1000"
"102000,1000"
]
)
start &68
end &1
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 119,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 120,0
va (VaSet
font "Arial,12,0"
)
xt "99000,-400,102100,1100"
st "outX"
blo "99000,800"
tm "WireNameMgr"
)
)
on &2
)
*81 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
)
xt "94750,3000,102000,3000"
pts [
"94750,3000"
"102000,3000"
]
)
start &70
end &3
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
font "Arial,12,0"
)
xt "99000,1600,102100,3100"
st "outY"
blo "99000,2800"
tm "WireNameMgr"
)
)
on &4
)
*82 (Wire
uid 5086,0
shape (OrthoPolyLine
uid 5087,0
va (VaSet
vasetType 3
)
xt "94750,7000,102000,7000"
pts [
"102000,7000"
"94750,7000"
]
)
start &5
end &71
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5090,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5091,0
va (VaSet
font "Arial,12,0"
)
xt "97000,5600,103500,7100"
st "selSinCos"
blo "97000,6800"
tm "WireNameMgr"
)
)
on &6
)
*83 (Wire
uid 15203,0
shape (OrthoPolyLine
uid 15204,0
va (VaSet
vasetType 3
)
xt "62750,1000,77250,1000"
pts [
"62750,1000"
"77250,1000"
]
)
start &49
end &67
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15205,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15206,0
va (VaSet
font "Arial,12,0"
)
xt "64750,-400,67250,1100"
st "run"
blo "64750,800"
tm "WireNameMgr"
)
)
on &8
)
*84 (Wire
uid 15209,0
shape (OrthoPolyLine
uid 15210,0
va (VaSet
vasetType 3
)
xt "62750,3000,77250,3000"
pts [
"62750,3000"
"77250,3000"
]
)
start &53
end &72
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15211,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15212,0
va (VaSet
font "Arial,12,0"
)
xt "64750,1600,73650,3100"
st "interpolateLin"
blo "64750,2800"
tm "WireNameMgr"
)
)
on &9
)
*85 (Wire
uid 15215,0
shape (OrthoPolyLine
uid 15216,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,5000,77250,5000"
pts [
"62750,5000"
"77250,5000"
]
)
start &50
end &73
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15217,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15218,0
va (VaSet
font "Arial,12,0"
)
xt "64750,3600,73550,5100"
st "updatePeriod"
blo "64750,4800"
tm "WireNameMgr"
)
)
on &10
)
*86 (Wire
uid 15464,0
shape (OrthoPolyLine
uid 15465,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,9000,77250,9000"
pts [
"62750,9000"
"77250,9000"
]
)
start &51
end &74
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15466,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15467,0
va (VaSet
font "Arial,12,0"
)
xt "64750,7600,69050,9100"
st "memX"
blo "64750,8800"
tm "WireNameMgr"
)
)
on &11
)
*87 (Wire
uid 15470,0
shape (OrthoPolyLine
uid 15471,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,11000,77250,11000"
pts [
"62750,11000"
"77250,11000"
]
)
start &52
end &75
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15472,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15473,0
va (VaSet
font "Arial,12,0"
)
xt "64750,9600,69050,11100"
st "memY"
blo "64750,10800"
tm "WireNameMgr"
)
)
on &12
)
*88 (Wire
uid 15576,0
shape (OrthoPolyLine
uid 15577,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "54000,-7000,62000,-3750"
pts [
"54000,-3750"
"54000,-7000"
"62000,-7000"
]
)
start &48
end &14
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15580,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15581,0
va (VaSet
font "Arial,12,0"
)
xt "57000,-8400,61600,-6900"
st "testOut"
blo "57000,-7200"
tm "WireNameMgr"
)
)
on &13
)
*89 (Wire
uid 16105,0
shape (OrthoPolyLine
uid 16106,0
va (VaSet
vasetType 3
)
xt "62750,7000,77250,7000"
pts [
"62750,7000"
"77250,7000"
]
)
start &55
end &76
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16107,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16108,0
va (VaSet
font "Arial,12,0"
)
xt "64750,5600,73250,7100"
st "newPolynom"
blo "64750,6800"
tm "WireNameMgr"
)
)
on &19
)
*90 (Wire
uid 16672,0
shape (OrthoPolyLine
uid 16673,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,1000,45250,1000"
pts [
"38000,1000"
"45250,1000"
]
)
start &20
end &46
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16676,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16677,0
va (VaSet
font "Arial,12,0"
)
xt "38000,-400,41900,1100"
st "hAddr"
blo "38000,800"
tm "WireNameMgr"
)
)
on &21
)
*91 (Wire
uid 16735,0
shape (OrthoPolyLine
uid 16736,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,3000,45250,3000"
pts [
"38000,3000"
"45250,3000"
]
)
start &22
end &56
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16739,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16740,0
va (VaSet
font "Arial,12,0"
)
xt "38000,1600,43100,3100"
st "hWData"
blo "38000,2800"
tm "WireNameMgr"
)
)
on &23
)
*92 (Wire
uid 16749,0
shape (OrthoPolyLine
uid 16750,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,11000,45250,11000"
pts [
"45250,11000"
"38000,11000"
]
)
start &47
end &24
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16753,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16754,0
va (VaSet
font "Arial,12,0"
)
xt "38000,9600,42900,11100"
st "hRData"
blo "38000,10800"
tm "WireNameMgr"
)
)
on &25
)
*93 (Wire
uid 16763,0
shape (OrthoPolyLine
uid 16764,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,5000,45250,5000"
pts [
"38000,5000"
"45250,5000"
]
)
start &26
end &57
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16768,0
va (VaSet
font "Arial,12,0"
)
xt "38000,3600,42600,5100"
st "hTrans"
blo "38000,4800"
tm "WireNameMgr"
)
)
on &27
)
*94 (Wire
uid 16777,0
shape (OrthoPolyLine
uid 16778,0
va (VaSet
vasetType 3
)
xt "38000,7000,45250,7000"
pts [
"38000,7000"
"45250,7000"
]
)
start &28
end &58
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16781,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16782,0
va (VaSet
font "Arial,12,0"
)
xt "38000,5600,42200,7100"
st "hWrite"
blo "38000,6800"
tm "WireNameMgr"
)
)
on &29
)
*95 (Wire
uid 16791,0
shape (OrthoPolyLine
uid 16792,0
va (VaSet
vasetType 3
)
xt "38000,9000,45250,9000"
pts [
"38000,9000"
"45250,9000"
]
)
start &30
end &59
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16795,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16796,0
va (VaSet
font "Arial,12,0"
)
xt "38000,7600,41200,9100"
st "hSel"
blo "38000,8800"
tm "WireNameMgr"
)
)
on &31
)
*96 (Wire
uid 16805,0
shape (OrthoPolyLine
uid 16806,0
va (VaSet
vasetType 3
)
xt "38000,13000,45250,13000"
pts [
"38000,13000"
"45250,13000"
]
)
start &39
end &60
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16809,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16810,0
va (VaSet
font "Arial,12,0"
)
xt "38000,11600,42900,13100"
st "hReady"
blo "38000,12800"
tm "WireNameMgr"
)
)
on &32
)
*97 (Wire
uid 16819,0
shape (OrthoPolyLine
uid 16820,0
va (VaSet
vasetType 3
)
xt "38000,15000,45250,15000"
pts [
"38000,15000"
"45250,15000"
]
)
start &38
end &61
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16823,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16824,0
va (VaSet
font "Arial,12,0"
)
xt "38000,13600,42400,15100"
st "hResp"
blo "38000,14800"
tm "WireNameMgr"
)
)
on &33
)
*98 (Wire
uid 16939,0
shape (OrthoPolyLine
uid 16940,0
va (VaSet
vasetType 3
)
xt "38000,19000,45250,19000"
pts [
"38000,19000"
"45250,19000"
]
)
start &34
end &45
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16943,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16944,0
va (VaSet
font "Arial,12,0"
)
xt "38000,17600,41200,19100"
st "hClk"
blo "38000,18800"
tm "WireNameMgr"
)
)
on &35
)
*99 (Wire
uid 16953,0
shape (OrthoPolyLine
uid 16954,0
va (VaSet
vasetType 3
)
xt "38000,21000,45250,21000"
pts [
"38000,21000"
"45250,21000"
]
)
start &36
end &54
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16957,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16958,0
va (VaSet
font "Arial,12,0"
)
xt "38000,19600,44100,21100"
st "hReset_n"
blo "38000,20800"
tm "WireNameMgr"
)
)
on &37
)
*100 (Wire
uid 17118,0
shape (OrthoPolyLine
uid 17119,0
va (VaSet
vasetType 3
)
xt "58000,25000,66000,25000"
pts [
"58000,25000"
"66000,25000"
]
)
end &40
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17124,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17125,0
va (VaSet
font "Arial,12,0"
)
xt "58000,23600,64100,25100"
st "hReset_n"
blo "58000,24800"
tm "WireNameMgr"
)
)
on &37
)
*101 (Wire
uid 17126,0
shape (OrthoPolyLine
uid 17127,0
va (VaSet
vasetType 3
)
xt "74000,17000,77250,25000"
pts [
"77250,17000"
"76000,17000"
"76000,25000"
"74000,25000"
]
)
start &69
end &40
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17132,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17133,0
va (VaSet
font "Arial,12,0"
)
xt "73000,15600,76500,17100"
st "reset"
blo "73000,16800"
tm "WireNameMgr"
)
)
on &7
)
*102 (Wire
uid 17242,0
shape (OrthoPolyLine
uid 17243,0
va (VaSet
vasetType 3
)
xt "74000,15000,77250,15000"
pts [
"74000,15000"
"77250,15000"
]
)
end &66
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17248,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17249,0
va (VaSet
font "Arial,12,0"
)
xt "74000,13600,77200,15100"
st "hClk"
blo "74000,14800"
tm "WireNameMgr"
)
)
on &35
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *103 (PackageList
uid 42,0
stg "VerticalLayoutStrategy"
textVec [
*104 (Text
uid 43,0
va (VaSet
font "Arial,8,1"
)
xt "0,-21000,5400,-20000"
st "Package List"
blo "0,-20200"
)
*105 (MLText
uid 44,0
va (VaSet
)
xt "0,-20000,17500,-14000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
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LIBRARY AhbLite;
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