295 lines
12 KiB
VHDL
295 lines
12 KiB
VHDL
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ARCHITECTURE test OF beamerSoc_tester IS
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-- clock and reset
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal sClock: std_uLogic := '1';
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signal sReset: std_uLogic := '1';
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-- register definition
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constant beamerBaseAddress: natural := 16#20#;
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constant beamerControlRegisterAddress: natural := beamerBaseAddress + 0;
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constant beamerControlRun: natural := 2#001#;
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constant beamerControlUpdatePattern: natural := 2#010#;
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constant beamerControlInterpolateLinear: natural := 2#100#;
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constant beamerControlsizeBase: natural := 16#80#;
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constant beamerSpeedRegisterAddress: natural := beamerBaseAddress + 1;
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constant beamerXFifoRegisterAddress: natural := beamerBaseAddress + 2;
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constant beamerYFifoRegisterAddress: natural := beamerBaseAddress + 3;
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-- microprocessor bus access
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constant registerWriteDelay: time := 4*clockPeriod;
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signal registerAddress: natural;
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signal registerDataOut, registerDataIn: integer;
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signal registerWrite, registerRead, registerDone: std_uLogic;
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-- UART access
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-- constant uartFrequency: real := 115200.0;
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constant uartDataBitNb: positive := 8;
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constant uartFrequency: real := 1.0E6;
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constant uartPeriod: time := (1.0/uartFrequency) * 1 sec;
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constant uartDataSpan: time := 10*uartPeriod;
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constant uartWriteReplySpan: time := 5*uartDataSpan;
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constant uartReadReplySpan: time := 10*uartDataSpan;
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signal uartRxData, uartTxData: integer;
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signal uartSend, uartDone: std_uLogic;
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signal uartTxShiftRegister: unsigned(2*uartDataBitNb-1 downto 0);
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signal uartTxDataWord: integer;
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BEGIN
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------------------------------------------------------------------------------
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-- clock and reset
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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reset <= '1', '0' after 2*clockPeriod;
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------------------------------------------------------------------------------
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-- test sequence
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process
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begin
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io <= (others => 'Z');
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selSinCos <= '0';
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wait for 1 ns;
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assert false
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report cr & cr & cr & cr &
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"----------------------------------------" &
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"----------------------------------------" &
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"----------------------------------------"
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severity note;
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----------------------------------------------------------------------------
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-- initialization by microprocessor
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wait for 100 ns - now;
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assert false
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report "Init" & cr & " --> " &
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"Letting the microprocessor initialize the peripherals"
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severity note;
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----------------------------------------------------------------------------
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-- test GPIOs
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wait for 400 ns - now;
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assert false
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report "GPIOs" & cr & " --> " &
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"Testing the GPIOs"
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severity note;
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io(7 downto 4) <= x"5";
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wait for 1 ns;
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assert io = x"5A"
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report "GPIO error"
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severity error;
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----------------------------------------------------------------------------
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-- set speed count value
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wait for 3*uartPeriod - now;
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assert false
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report "Beamer init" & cr & " --> " &
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"Setting drawing speed"
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severity note;
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registerAddress <= beamerSpeedRegisterAddress;
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registerDataOut <= 2;
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--registerAddress <= 16#1234#;
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--registerDataOut <= 16#5678#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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----------------------------------------------------------------------------
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-- start updating pattern
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assert false
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report "Beamer init" & cr & " --> " &
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"Writing y-pattern to beamer RAM"
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severity note;
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registerAddress <= beamerControlRegisterAddress;
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registerDataOut <= beamerControlUpdatePattern;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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----------------------------------------------------------------------------
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-- write y-FIFO
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registerAddress <= beamerYFifoRegisterAddress;
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registerDataOut <= -16#4000# + 16#10000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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registerDataOut <= 16#7000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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registerDataOut <= 16#7000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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registerDataOut <= -16#7000# + 16#10000#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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----------------------------------------------------------------------------
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-- start run
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assert false
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report "Beamer play" & cr & " --> " &
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"Launching pattern drawing (setting pattern size and run flag)"
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severity note;
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registerAddress <= beamerControlRegisterAddress;
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registerDataOut <= beamerControlRun + beamerControlsizeBase * 4;
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registerWrite <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartWriteReplySpan;
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----------------------------------------------------------------------------
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-- readback control register
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assert false
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report "Beamer test" & cr & " --> " &
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"Reading back control register"
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severity note;
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registerAddress <= beamerControlRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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wait for uartPeriod;
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wait until registerDone = '1';
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wait for uartReadReplySpan;
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assert uartTxDataWord = beamerControlRun + beamerControlsizeBase * 4
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report "Beamer register readback error"
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severity error;
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----------------------------------------------------------------------------
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-- stop simulation
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wait for 1.5 ms - now;
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assert false
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report "End" & cr & " --> " &
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"End of simulation"
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severity failure;
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end process;
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--============================================================================
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-- microprocessor bus access
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busAccess: process
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variable writeAccess: boolean;
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-- variable packetId: natural := 0;
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variable packetId: natural := 16#1D#;
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variable checksum: natural;
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begin
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registerDone <= '1';
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uartSend <= '0';
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uartRxData <= 16#AA#;
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wait on registerWrite, registerRead;
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registerDone <= '0';
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writeAccess := false;
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if registerWrite = '1' then
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writeAccess := true;
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end if;
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-- send header
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := uartRxData;
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-- send packet id
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uartRxData <= packetId;
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packetId := (packetId + 1) mod 2**8;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send command
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if writeAccess then
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uartRxData <= 16#03#;
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else
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uartRxData <= 16#04#;
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end if;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send data length
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if writeAccess then
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uartRxData <= 4;
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else
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uartRxData <= 2;
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end if;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send addresss low
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uartRxData <= registerAddress mod 2**8;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send addresss high
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uartRxData <= registerAddress / 2**8;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send data low
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if writeAccess then
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uartRxData <= registerDataOut mod 2**8;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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-- send data high
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uartRxData <= registerDataOut / 2**8;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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checksum := (checksum + uartRxData) mod 2**8;
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end if;
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-- send checksum
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uartRxData <= checksum;
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uartSend <= '1', '0' after uartPeriod;
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wait for uartPeriod;
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wait until uartDone = '1';
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end process;
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------------------------------------------------------------------------------
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-- UART access
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sendByte: process
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variable serialData: unsigned(7 downto 0);
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begin
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-- send stop bit
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uartDone <= '1';
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RxD <= '1';
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-- get new word
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wait until rising_edge(uartSend);
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uartDone <= '0';
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serialData := to_unsigned(uartRxData, serialData'length);
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-- send start bit
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RxD <= '0';
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wait for uartPeriod;
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-- send data bits
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for index in serialData'reverse_range loop
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RxD <= serialData(index);
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wait for uartPeriod;
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end loop;
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-- send stop bits
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RxD <= '1';
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wait for 4*uartPeriod;
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end process sendByte;
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------------------------------------------------------------------------------
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-- UART access
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receiveByte: process
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variable serialData: unsigned(uartDataBitNb-1 downto 0);
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begin
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-- wait for stat bit
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wait until falling_edge(TxD);
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-- jump to middle of first data bit
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wait for 1.5 * uartPeriod;
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-- read data bits
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for index in serialData'reverse_range loop
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if Is_X(TxD) then
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serialData(index) := '0';
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else
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serialData(index) := TxD;
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end if;
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wait for uartPeriod;
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end loop;
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-- write data to signal
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uartTxData <= to_integer(serialData);
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uartTxDataWord <= to_integer(uartTxShiftRegister);
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uartTxShiftRegister <= shift_right(uartTxShiftRegister, serialData'length);
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uartTxShiftRegister(
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uartTxShiftRegister'high downto
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uartTxShiftRegister'high-serialData'length+1
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) <= serialData;
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end process receiveByte;
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END ARCHITECTURE test;
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