29 lines
903 B
VHDL
29 lines
903 B
VHDL
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ARCHITECTURE masterVersion OF interpolatorCoefficients IS
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BEGIN
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calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4)
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begin
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if interpolateLinear = '1' then
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a <= (others => '0');
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b <= (others => '0');
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c <= resize(2*sample3, c'length)
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- resize(2*sample2, c'length);
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d <= resize( sample2, d'length);
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else
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a <= resize( sample4, a'length)
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- resize(3*sample3, a'length)
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+ resize(3*sample2, a'length)
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- resize( sample1, a'length);
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b <= resize(2*sample1, b'length)
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- resize(5*sample2, b'length)
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+ resize(4*sample3, b'length)
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- resize( sample4, b'length);
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c <= resize( sample3, c'length)
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- resize( sample1, c'length);
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d <= resize( sample2, d'length);
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end if;
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end process calcCoeffs;
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END ARCHITECTURE masterVersion;
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