28 lines
575 B
VHDL
28 lines
575 B
VHDL
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ARCHITECTURE masterVersion OF interpolatorTrigger IS
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signal triggerCounter: unsigned(counterBitNb-1 downto 0);
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BEGIN
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count: process(reset, clock)
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begin
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if reset = '1' then
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triggerCounter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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triggerCounter <= triggerCounter + 1;
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end if;
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end if;
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end process count;
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trig: process(triggerCounter, en)
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begin
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if triggerCounter = 0 then
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triggerOut <= en;
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else
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triggerOut <= '0';
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end if;
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end process trig;
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END ARCHITECTURE masterVersion;
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