35 lines
1.0 KiB
Plaintext
35 lines
1.0 KiB
Plaintext
|
-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
|
||
|
|
--
|
||
|
|
-- Created:
|
||
|
|
-- by - francois.francois (Aphelia)
|
||
|
|
-- at - 13:00:14 02/19/19
|
||
|
|
--
|
||
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||
|
|
--
|
||
|
|
LIBRARY ieee;
|
||
|
|
USE ieee.std_logic_1164.all;
|
||
|
|
USE ieee.numeric_std.all;
|
||
|
|
|
||
|
|
ENTITY interpolatorCalculatePolynom IS
|
||
|
|
GENERIC(
|
||
|
|
signalBitNb : positive := 16;
|
||
|
|
coeffBitNb : positive := 16;
|
||
|
|
oversamplingBitNb : positive := 8
|
||
|
|
);
|
||
|
|
PORT(
|
||
|
|
clock : IN std_ulogic;
|
||
|
|
reset : IN std_ulogic;
|
||
|
|
restartPolynom : IN std_ulogic;
|
||
|
|
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
||
|
|
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
||
|
|
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
||
|
|
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
||
|
|
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
||
|
|
en : IN std_ulogic
|
||
|
|
);
|
||
|
|
|
||
|
|
-- Declarations
|
||
|
|
|
||
|
|
END interpolatorCalculatePolynom ;
|
||
|
|
|