15 lines
197 B
VHDL
15 lines
197 B
VHDL
|
ARCHITECTURE sim OF DFF IS
|
||
|
|
BEGIN
|
||
|
|
|
||
|
|
process(clk, clr)
|
||
|
|
begin
|
||
|
|
if clr = '1' then
|
||
|
|
q <= '0';
|
||
|
|
elsif rising_edge(clk) then
|
||
|
|
q <= d;
|
||
|
|
end if;
|
||
|
|
end process;
|
||
|
|
|
||
|
|
END ARCHITECTURE sim;
|
||
|
|
|