SEm-Labos/10-PipelinedOperators/PipelinedOperators_test/hds/parallel@adder_tb/struct.bd

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tm "PanelText"
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tm "CptNameMgr"
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tm "WireNameMgr"
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xt "500,-375,2000,375"
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ro 270
xt "0,0,500,0"
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tm "WireNameMgr"
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defaultPortIoInOut (PortIoInOut
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fg "0,0,32768"
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xt "500,-375,2000,375"
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(Line
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xt "0,0,500,0"
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)
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tg (WTG
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
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defaultPortIoBuffer (PortIoBuffer
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(Line
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xt "0,0,500,0"
pts [
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)
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)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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font "Verdana,12,0"
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blo "0,-375"
tm "WireNameMgr"
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)
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shape (OrthoPolyLine
va (VaSet
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ss 0
es 0
sat 32
eat 32
stc 0
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tg (WTG
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tm "WireNameMgr"
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sat 32
eat 32
sty 1
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tm "WireNameMgr"
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sat 32
eat 32
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tm "PortMapTextMgr"
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)
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lineStyle 2
lineWidth 3
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text (MLText
va (VaSet
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fg "65535,65535,65535"
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xt "50,50,1050,1450"
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num (Text
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tm "FrameSeqNumMgr"
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va (VaSet
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thePort (LogicalPort
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thePort (LogicalPort
m 3
decl (Decl
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t ""
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