SEm-Labos/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@adder_tb/struct.bd

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
]
instances [
(Instance
name "I_tester"
duLibraryName "pipelinedOperators_test"
duName "pipelineAdder_tester"
elements [
(GiElement
name "adderBitNb"
type "positive"
value "adderBitNb"
)
(GiElement
name "stageNb"
type "positive"
value "pipelineStageNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
mwi 0
uid 2178,0
)
(Instance
name "I_DUT"
duLibraryName "pipelinedOperators"
duName "pipelineAdder"
elements [
(GiElement
name "bitNb"
type "positive"
value "adderBitNb"
)
(GiElement
name "stageNb"
type "positive"
value "pipelineStageNb"
)
]
mwi 0
uid 2359,0
)
]
libraryRefs [
"ieee"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineAdder_tb"
)
(vvPair
variable "date"
value "28.04.2023"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "pipelineAdder_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "28.04.2023"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "15:20:22"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "PipelinedOperators_test"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/PipelinedOperators_test"
)
(vvPair
variable "mm"
value "04"
)
(vvPair
variable "module_name"
value "pipelineAdder_tb"
)
(vvPair
variable "month"
value "avr."
)
(vvPair
variable "month_long"
value "avril"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@adder_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineAdder_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "/usr/opt/Modelsim/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "15:20:22"
)
(vvPair
variable "unit"
value "pipelineAdder_tb"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2023"
)
(vvPair
variable "yy"
value "23"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 153,0
optionalChildren [
*1 (Grouping
uid 110,0
optionalChildren [
*2 (CommentText
uid 112,0
shape (Rectangle
uid 113,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,48000,53000,49000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 114,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,48500,36200,48500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 115,0
shape (Rectangle
uid 116,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,44000,57000,45000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 117,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,44500,53200,44500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 118,0
shape (Rectangle
uid 119,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,46000,53000,47000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 120,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,46500,36200,46500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 121,0
shape (Rectangle
uid 122,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,46000,36000,47000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 123,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,46500,32200,46500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 124,0
shape (Rectangle
uid 125,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,45000,73000,49000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 126,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "53200,45200,67300,46400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*7 (CommentText
uid 127,0
shape (Rectangle
uid 128,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "57000,44000,73000,45000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 129,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "57200,44500,57200,44500"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 130,0
shape (Rectangle
uid 131,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,44000,53000,46000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 132,0
va (VaSet
fg "32768,0,0"
)
xt "37350,44400,47650,45600"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 133,0
shape (Rectangle
uid 134,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,47000,36000,48000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 135,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,47500,32200,47500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
uid 136,0
shape (Rectangle
uid 137,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "32000,48000,36000,49000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 138,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "32200,48500,32200,48500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 139,0
shape (Rectangle
uid 140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "36000,47000,53000,48000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "36200,47500,36200,47500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 111,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "32000,44000,73000,49000"
)
oxt "14000,66000,55000,71000"
)
*12 (Blk
uid 2178,0
shape (Rectangle
uid 2179,0
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "16000,30000,60000,38000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 2180,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*13 (Text
uid 2181,0
va (VaSet
)
xt "15850,38200,27850,39100"
st "pipelinedOperators_test"
blo "15850,38900"
tm "BdLibraryNameMgr"
)
*14 (Text
uid 2182,0
va (VaSet
)
xt "15850,39400,26350,40300"
st "pipelineAdder_tester"
blo "15850,40100"
tm "BlkNameMgr"
)
*15 (Text
uid 2183,0
va (VaSet
)
xt "15850,40600,19850,41500"
st "I_tester"
blo "15850,41300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2184,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2185,0
text (MLText
uid 2186,0
va (VaSet
)
xt "16000,42000,42500,45600"
st "adderBitNb     = adderBitNb         ( positive )  
stageNb        = pipelineStageNb    ( positive )  
clockFrequency = clockFrequency     ( real     )  
"
)
header ""
)
elements [
(GiElement
name "adderBitNb"
type "positive"
value "adderBitNb"
)
(GiElement
name "stageNb"
type "positive"
value "pipelineStageNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
)
)
*16 (Net
uid 2224,0
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 18,0
)
declText (MLText
uid 2225,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,18200,13700,19200"
st "SIGNAL reset : std_ulogic"
)
)
*17 (Net
uid 2232,0
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 19,0
)
declText (MLText
uid 2233,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,17200,13700,18200"
st "SIGNAL clock : std_ulogic"
)
)
*18 (Net
uid 2240,0
decl (Decl
n "cOut"
t "std_ulogic"
o 4
suid 20,0
)
declText (MLText
uid 2241,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,16200,13800,17200"
st "SIGNAL cOut  : std_ulogic"
)
)
*19 (Net
uid 2248,0
decl (Decl
n "cIn"
t "std_ulogic"
o 3
suid 21,0
)
declText (MLText
uid 2249,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,15200,13500,16200"
st "SIGNAL cIn   : std_ulogic"
)
)
*20 (Net
uid 2256,0
decl (Decl
n "b"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 2
suid 22,0
)
declText (MLText
uid 2257,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,14200,23400,15200"
st "SIGNAL b     : signed(adderBitNb-1 DOWNTO 0)"
)
)
*21 (Net
uid 2264,0
decl (Decl
n "a"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 1
suid 23,0
)
declText (MLText
uid 2265,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,13200,23400,14200"
st "SIGNAL a     : signed(adderBitNb-1 DOWNTO 0)"
)
)
*22 (Net
uid 2284,0
decl (Decl
n "sum"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 7
suid 24,0
)
declText (MLText
uid 2285,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,19200,24000,20200"
st "SIGNAL sum   : signed(adderBitNb-1 DOWNTO 0)"
)
)
*23 (SaComponent
uid 2359,0
optionalChildren [
*24 (CptPort
uid 2331,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2332,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37625,22000,38375,22750"
)
tg (CPTG
uid 2333,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2334,0
va (VaSet
)
xt "37000,20800,38500,21700"
st "sum"
blo "37000,21500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sum"
t "signed"
b "(bitNb-1 downto 0)"
o 1
suid 1,0
)
)
)
*25 (CptPort
uid 2335,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2336,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33250,19625,34000,20375"
)
tg (CPTG
uid 2337,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2338,0
va (VaSet
)
xt "35000,19400,37500,20300"
st "clock"
blo "35000,20100"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*26 (CptPort
uid 2339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2340,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33917,20625,34667,21375"
)
tg (CPTG
uid 2341,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2342,0
va (VaSet
)
xt "35667,20400,38167,21300"
st "reset"
blo "35667,21100"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*27 (CptPort
uid 2343,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2344,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43334,17625,44084,18375"
)
tg (CPTG
uid 2345,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2346,0
va (VaSet
)
xt "40834,17400,42334,18300"
st "cIn"
ju 2
blo "42334,18100"
)
)
thePort (LogicalPort
decl (Decl
n "cIn"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*28 (CptPort
uid 2347,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2348,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31917,17625,32667,18375"
)
tg (CPTG
uid 2349,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2350,0
va (VaSet
)
xt "33667,17400,35667,18300"
st "cOut"
blo "33667,18100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cOut"
t "std_ulogic"
o 5
suid 2005,0
)
)
)
*29 (CptPort
uid 2351,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2352,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "33625,13250,34375,14000"
)
tg (CPTG
uid 2353,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2354,0
va (VaSet
)
xt "33800,14000,34300,14900"
st "a"
ju 2
blo "34300,14700"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(bitNb-1 downto 0)"
o 6
suid 2006,0
)
)
)
*30 (CptPort
uid 2355,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2356,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41625,13250,42375,14000"
)
tg (CPTG
uid 2357,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2358,0
va (VaSet
)
xt "41800,14000,42300,14900"
st "b"
ju 2
blo "42300,14700"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(bitNb-1 downto 0)"
o 7
suid 2007,0
)
)
)
]
shape (Alu
uid 2360,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "30000,14000,46000,22000"
)
oxt "32000,15000,48000,23000"
ttg (MlTextGroup
uid 2361,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*31 (Text
uid 2362,0
va (VaSet
font "Verdana,9,1"
)
xt "39600,21800,49100,22700"
st "pipelinedOperators"
blo "39600,22500"
tm "BdLibraryNameMgr"
)
*32 (Text
uid 2363,0
va (VaSet
font "Verdana,9,1"
)
xt "39600,23000,46600,23900"
st "pipelineAdder"
blo "39600,23700"
tm "CptNameMgr"
)
*33 (Text
uid 2364,0
va (VaSet
font "Verdana,9,1"
)
xt "39600,24200,42100,25100"
st "I_DUT"
blo "39600,24900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2365,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2366,0
text (MLText
uid 2367,0
va (VaSet
font "Verdana,8,0"
)
xt "40000,25600,59400,27600"
st "bitNb   = adderBitNb         ( positive )  
stageNb = pipelineStageNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "adderBitNb"
)
(GiElement
name "stageNb"
type "positive"
value "pipelineStageNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*34 (Wire
uid 2226,0
shape (OrthoPolyLine
uid 2227,0
va (VaSet
vasetType 3
)
xt "30000,21000,33917,30000"
pts [
"33917,21000"
"30000,21000"
"30000,30000"
]
)
start &26
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2230,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2231,0
va (VaSet
font "Verdana,12,0"
)
xt "28917,19600,33017,21000"
st "reset"
blo "28917,20800"
tm "WireNameMgr"
)
)
on &16
)
*35 (Wire
uid 2234,0
shape (OrthoPolyLine
uid 2235,0
va (VaSet
vasetType 3
)
xt "28000,20000,33250,30000"
pts [
"33250,20000"
"28000,20000"
"28000,30000"
]
)
start &25
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2238,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2239,0
va (VaSet
font "Verdana,12,0"
)
xt "28250,18600,32050,20000"
st "clock"
blo "28250,19800"
tm "WireNameMgr"
)
)
on &17
)
*36 (Wire
uid 2242,0
shape (OrthoPolyLine
uid 2243,0
va (VaSet
vasetType 3
)
xt "24000,18000,31917,30000"
pts [
"31917,18000"
"24000,18000"
"24000,30000"
]
)
start &28
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2246,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2247,0
va (VaSet
font "Verdana,12,0"
)
xt "26917,16600,30617,18000"
st "cOut"
blo "26917,17800"
tm "WireNameMgr"
)
)
on &18
)
*37 (Wire
uid 2250,0
shape (OrthoPolyLine
uid 2251,0
va (VaSet
vasetType 3
)
xt "44084,18000,48000,30000"
pts [
"44084,18000"
"48000,18000"
"48000,30000"
]
)
start &27
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2254,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2255,0
va (VaSet
font "Verdana,12,0"
)
xt "46084,16600,48784,18000"
st "cIn"
blo "46084,17800"
tm "WireNameMgr"
)
)
on &19
)
*38 (Wire
uid 2258,0
shape (OrthoPolyLine
uid 2259,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "42000,10000,50000,30000"
pts [
"42000,13250"
"42000,10000"
"50000,10000"
"50000,30000"
]
)
start &30
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2262,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2263,0
va (VaSet
font "Verdana,12,0"
)
xt "40500,10350,42100,11750"
st "b"
blo "40500,11550"
tm "WireNameMgr"
)
)
on &20
)
*39 (Wire
uid 2266,0
shape (OrthoPolyLine
uid 2267,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "34000,8000,52000,30000"
pts [
"34000,13250"
"34000,8000"
"52000,8000"
"52000,30000"
]
)
start &29
end &12
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2270,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2271,0
va (VaSet
font "Verdana,12,0"
)
xt "32500,10350,34100,11750"
st "a"
blo "32500,11550"
tm "WireNameMgr"
)
)
on &21
)
*40 (Wire
uid 2286,0
shape (OrthoPolyLine
uid 2287,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,22750,38000,30000"
pts [
"38000,22750"
"38000,30000"
]
)
start &24
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2290,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2291,0
va (VaSet
font "Verdana,12,0"
)
xt "35000,26600,37100,27900"
st "sum"
blo "35000,27600"
tm "WireNameMgr"
)
)
on &22
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *41 (PackageList
uid 142,0
stg "VerticalLayoutStrategy"
textVec [
*42 (Text
uid 143,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6500,900"
st "Package List"
blo "0,700"
)
*43 (MLText
uid 144,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 145,0
stg "VerticalLayoutStrategy"
textVec [
*44 (Text
uid 146,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30000,900"
st "Compiler Directives"
blo "20000,700"
)
*45 (Text
uid 147,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,31500,1900"
st "Pre-module directives:"
blo "20000,1700"
)
*46 (MLText
uid 148,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*47 (Text
uid 149,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32000,4900"
st "Post-module directives:"
blo "20000,4700"
)
*48 (MLText
uid 150,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*49 (Text
uid 151,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,31500,5900"
st "End-module directives:"
blo "20000,5700"
)
*50 (MLText
uid 152,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-1064,-1064,93573,50355"
cachedDiagramExtent "0,0,73000,49000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\ipp://ipp.hevs.ch\\PREA309_HPLJP3005DN,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
windowsPaperType 9
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 2663,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*51 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*52 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*53 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*54 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*55 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*56 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*57 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*58 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*59 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*60 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*61 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*62 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*64 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*65 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*67 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*68 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*69 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*71 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,5600,6500,6500"
st "Declarations"
blo "0,6300"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,6500,3000,7400"
st "Ports:"
blo "0,7200"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,7400,4500,8300"
st "Pre User:"
blo "0,8100"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,8300,22100,12300"
st "constant adderBitNb: positive := 32;
constant pipelineStageNb: positive := 4;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "0,12300,8500,13200"
st "Diagram Signals:"
blo "0,13000"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,5600,5500,6500"
st "Post User:"
blo "0,6300"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,5600,0,5600"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 24,0
usingSuid 1
emptyRow *72 (LEmptyRow
)
uid 1321,0
optionalChildren [
*73 (RefLabelRowHdr
)
*74 (TitleRowHdr
)
*75 (FilterRowHdr
)
*76 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*77 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*78 (GroupColHdr
tm "GroupColHdrMgr"
)
*79 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*80 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*81 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*82 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*83 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*84 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*85 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 18,0
)
)
uid 2272,0
)
*86 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 19,0
)
)
uid 2274,0
)
*87 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cOut"
t "std_ulogic"
o 4
suid 20,0
)
)
uid 2276,0
)
*88 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cIn"
t "std_ulogic"
o 3
suid 21,0
)
)
uid 2278,0
)
*89 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "b"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 2
suid 22,0
)
)
uid 2280,0
)
*90 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "a"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 1
suid 23,0
)
)
uid 2282,0
)
*91 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sum"
t "signed"
b "(adderBitNb-1 DOWNTO 0)"
o 7
suid 24,0
)
)
uid 2292,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 1334,0
optionalChildren [
*92 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *93 (MRCItem
litem &72
pos 7
dimension 20
)
uid 1336,0
optionalChildren [
*94 (MRCItem
litem &73
pos 0
dimension 20
uid 1337,0
)
*95 (MRCItem
litem &74
pos 1
dimension 23
uid 1338,0
)
*96 (MRCItem
litem &75
pos 2
hidden 1
dimension 20
uid 1339,0
)
*97 (MRCItem
litem &85
pos 0
dimension 20
uid 2273,0
)
*98 (MRCItem
litem &86
pos 1
dimension 20
uid 2275,0
)
*99 (MRCItem
litem &87
pos 2
dimension 20
uid 2277,0
)
*100 (MRCItem
litem &88
pos 3
dimension 20
uid 2279,0
)
*101 (MRCItem
litem &89
pos 4
dimension 20
uid 2281,0
)
*102 (MRCItem
litem &90
pos 5
dimension 20
uid 2283,0
)
*103 (MRCItem
litem &91
pos 6
dimension 20
uid 2293,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1340,0
optionalChildren [
*104 (MRCItem
litem &76
pos 0
dimension 20
uid 1341,0
)
*105 (MRCItem
litem &78
pos 1
dimension 50
uid 1342,0
)
*106 (MRCItem
litem &79
pos 2
dimension 100
uid 1343,0
)
*107 (MRCItem
litem &80
pos 3
dimension 50
uid 1344,0
)
*108 (MRCItem
litem &81
pos 4
dimension 100
uid 1345,0
)
*109 (MRCItem
litem &82
pos 5
dimension 100
uid 1346,0
)
*110 (MRCItem
litem &83
pos 6
dimension 50
uid 1347,0
)
*111 (MRCItem
litem &84
pos 7
dimension 80
uid 1348,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 1335,0
vaOverrides [
]
)
]
)
uid 1320,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *112 (LEmptyRow
)
uid 1350,0
optionalChildren [
*113 (RefLabelRowHdr
)
*114 (TitleRowHdr
)
*115 (FilterRowHdr
)
*116 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*117 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*118 (GroupColHdr
tm "GroupColHdrMgr"
)
*119 (NameColHdr
tm "GenericNameColHdrMgr"
)
*120 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*121 (InitColHdr
tm "GenericValueColHdrMgr"
)
*122 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*123 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 1362,0
optionalChildren [
*124 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *125 (MRCItem
litem &112
pos 0
dimension 20
)
uid 1364,0
optionalChildren [
*126 (MRCItem
litem &113
pos 0
dimension 20
uid 1365,0
)
*127 (MRCItem
litem &114
pos 1
dimension 23
uid 1366,0
)
*128 (MRCItem
litem &115
pos 2
hidden 1
dimension 20
uid 1367,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 1368,0
optionalChildren [
*129 (MRCItem
litem &116
pos 0
dimension 20
uid 1369,0
)
*130 (MRCItem
litem &118
pos 1
dimension 50
uid 1370,0
)
*131 (MRCItem
litem &119
pos 2
dimension 100
uid 1371,0
)
*132 (MRCItem
litem &120
pos 3
dimension 100
uid 1372,0
)
*133 (MRCItem
litem &121
pos 4
dimension 50
uid 1373,0
)
*134 (MRCItem
litem &122
pos 5
dimension 50
uid 1374,0
)
*135 (MRCItem
litem &123
pos 6
dimension 80
uid 1375,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 1363,0
vaOverrides [
]
)
]
)
uid 1349,0
type 1
)
activeModelName "BlockDiag"
)