19 lines
444 B
VHDL
19 lines
444 B
VHDL
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ARCHITECTURE RTL OF ahbMultiplexor IS
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BEGIN
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multiplexData: process(hSel, hRDataV, hReadyV, hRespV)
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begin
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hRData <= (others => '0');
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hReady <= '1';
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hResp <= '0';
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for index in hSel'range loop
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if hSel(index) = '1' then
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hRData <= std_ulogic_vector(hRDataV(index));
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hReady <= hReadyV(index);
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hResp <= hRespV(index);
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end if;
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end loop;
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end process multiplexData;
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END ARCHITECTURE RTL;
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