48 lines
1.6 KiB
VHDL
48 lines
1.6 KiB
VHDL
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ARCHITECTURE test OF rotaryToUnsigned_tester IS
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constant clockFrequency : real := 100.0E6;
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constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
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signal clock_int : std_ulogic := '1';
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constant stepPeriod : time := 100*clockPeriod;
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signal rotary_int : unsigned(rotary'range);
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 3*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- input signal
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turnRotary: process
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begin
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rotary_int <= (others => '0');
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wait for 10*stepPeriod;
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-- count over max value
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for index in 1 to 2**outputBitNb+2 loop
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rotary_int <= rotary_int + 1;
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wait for stepPeriod;
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end loop;
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-- count down again
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for index in 1 to 2**outputBitNb+2 loop
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rotary_int <= rotary_int - 1;
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wait for stepPeriod;
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end loop;
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-- end of simulation
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wait;
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end process turnRotary;
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addGlitches: process
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begin
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wait on rotary_int;
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rotary <= (others => '0');
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wait for clockPeriod;
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rotary <= (others => '1');
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wait for clockPeriod;
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rotary <= rotary_int;
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end process addGlitches;
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END ARCHITECTURE test;
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