25 lines
491 B
VHDL
25 lines
491 B
VHDL
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ARCHITECTURE RTL OF rs232Mux IS
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signal passThrough: std_ulogic;
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BEGIN
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passThrough <= not selOther;
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multiplexer: process(passThrough, txData, txFullF, TxWr, otherData, otherWr)
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begin
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if passThrough = '1' then
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txDataF <= txData;
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txWrF <= TxWr;
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txFull <= txFullF;
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otherFull <= '1';
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else
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txDataF <= otherData;
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txWrF <= otherWr;
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otherFull <= txFullF;
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txFull <= '1';
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end if;
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end process multiplexer;
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END ARCHITECTURE RTL;
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