78 lines
2.3 KiB
VHDL
78 lines
2.3 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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entity uart_rx_simple is
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generic (
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name : string;
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uart_baud_val_c : real);
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port (
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clk : in std_ulogic;
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uart_txd : in std_ulogic
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);
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end entity;
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architecture a of uart_rx_simple is
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart_rx_baud_cnt : real;
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signal uart_rx_bitcnt : natural;
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & name & ".out";
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begin
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uart_rx_console : process(clk)
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variable i : integer;
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variable l : line;
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begin
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-- "UART" --
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if rising_edge(clk) then
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-- synchronizer --
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uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
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-- arbiter --
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if (uart_rx_busy = '0') then -- idle
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uart_rx_busy <= '0';
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uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
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uart_rx_bitcnt <= 9;
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if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart_rx_busy <= '1';
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end if;
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else
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if (uart_rx_baud_cnt <= 0.0) then
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if (uart_rx_bitcnt = 1) then
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uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
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else
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uart_rx_baud_cnt <= round(uart_baud_val_c);
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end if;
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if (uart_rx_bitcnt = 0) then
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uart_rx_busy <= '0'; -- done
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i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
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if (i < 32) or (i > 32+95) then -- printable char?
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report name & ".tx: (" & integer'image(i) & ")"; -- print code
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else
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report name & ".tx: " & character'val(i); -- print ASCII
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end if;
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if (i = 10) then -- Linux line break
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writeline(file_uart_tx_out, l);
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elsif (i /= 13) then -- Remove additional carriage return
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write(l, character'val(i));
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end if;
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else
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uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
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uart_rx_bitcnt <= uart_rx_bitcnt - 1;
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end if;
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else
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uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
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end if;
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end if;
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end if;
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end process uart_rx_console;
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end architecture;
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