1604 lines
20 KiB
Plaintext
1604 lines
20 KiB
Plaintext
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DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "24.1"
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appVersion "2009.2 (Build 10)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2007,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 158,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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decl (Decl
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n "cIn"
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t "std_ulogic"
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o 2
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suid 4,0
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)
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)
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uid 161,0
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)
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*3 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "sum"
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t "signed"
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|
b "(bitNb-1 downto 0)"
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o 1
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suid 1,0
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)
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)
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|
uid 162,0
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)
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*4 (RefLabelRowHdr
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)
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*5 (TitleRowHdr
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)
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||
|
*6 (FilterRowHdr
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||
|
)
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||
|
*7 (RefLabelColHdr
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||
|
tm "RefLabelColHdrMgr"
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||
|
)
|
||
|
*8 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
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||
|
)
|
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|
*9 (GroupColHdr
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|
tm "GroupColHdrMgr"
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|
)
|
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|
*10 (NameColHdr
|
||
|
tm "NameColHdrMgr"
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||
|
)
|
||
|
*11 (ModeColHdr
|
||
|
tm "ModeColHdrMgr"
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||
|
)
|
||
|
*12 (TypeColHdr
|
||
|
tm "TypeColHdrMgr"
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||
|
)
|
||
|
*13 (BoundsColHdr
|
||
|
tm "BoundsColHdrMgr"
|
||
|
)
|
||
|
*14 (InitColHdr
|
||
|
tm "InitColHdrMgr"
|
||
|
)
|
||
|
*15 (EolColHdr
|
||
|
tm "EolColHdrMgr"
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||
|
)
|
||
|
*16 (LogPort
|
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
|
||
|
n "cOut"
|
||
|
t "std_ulogic"
|
||
|
o 3
|
||
|
suid 2005,0
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||
|
)
|
||
|
)
|
||
|
uid 197,0
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||
|
)
|
||
|
*17 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "a"
|
||
|
t "signed"
|
||
|
b "(bitNb-1 downto 0)"
|
||
|
o 4
|
||
|
suid 2006,0
|
||
|
)
|
||
|
)
|
||
|
uid 209,0
|
||
|
)
|
||
|
*18 (LogPort
|
||
|
port (LogicalPort
|
||
|
decl (Decl
|
||
|
n "b"
|
||
|
t "signed"
|
||
|
b "(bitNb-1 downto 0)"
|
||
|
o 5
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||
|
suid 2007,0
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||
|
)
|
||
|
)
|
||
|
uid 211,0
|
||
|
)
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|
]
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||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 163,0
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||
|
optionalChildren [
|
||
|
*19 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
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||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
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||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
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||
|
)
|
||
|
emptyMRCItem *20 (MRCItem
|
||
|
litem &1
|
||
|
pos 5
|
||
|
dimension 20
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||
|
)
|
||
|
uid 100,0
|
||
|
optionalChildren [
|
||
|
*21 (MRCItem
|
||
|
litem &4
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||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 103,0
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||
|
)
|
||
|
*22 (MRCItem
|
||
|
litem &5
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||
|
pos 1
|
||
|
dimension 23
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||
|
uid 105,0
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||
|
)
|
||
|
*23 (MRCItem
|
||
|
litem &6
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 107,0
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||
|
)
|
||
|
*24 (MRCItem
|
||
|
litem &2
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
uid 128,0
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||
|
)
|
||
|
*25 (MRCItem
|
||
|
litem &3
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 129,0
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||
|
)
|
||
|
*26 (MRCItem
|
||
|
litem &16
|
||
|
pos 2
|
||
|
dimension 20
|
||
|
uid 198,0
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||
|
)
|
||
|
*27 (MRCItem
|
||
|
litem &17
|
||
|
pos 3
|
||
|
dimension 20
|
||
|
uid 210,0
|
||
|
)
|
||
|
*28 (MRCItem
|
||
|
litem &18
|
||
|
pos 4
|
||
|
dimension 20
|
||
|
uid 212,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 101,0
|
||
|
optionalChildren [
|
||
|
*29 (MRCItem
|
||
|
litem &7
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 109,0
|
||
|
)
|
||
|
*30 (MRCItem
|
||
|
litem &9
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 113,0
|
||
|
)
|
||
|
*31 (MRCItem
|
||
|
litem &10
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 115,0
|
||
|
)
|
||
|
*32 (MRCItem
|
||
|
litem &11
|
||
|
pos 3
|
||
|
dimension 50
|
||
|
uid 117,0
|
||
|
)
|
||
|
*33 (MRCItem
|
||
|
litem &12
|
||
|
pos 4
|
||
|
dimension 100
|
||
|
uid 119,0
|
||
|
)
|
||
|
*34 (MRCItem
|
||
|
litem &13
|
||
|
pos 5
|
||
|
dimension 100
|
||
|
uid 121,0
|
||
|
)
|
||
|
*35 (MRCItem
|
||
|
litem &14
|
||
|
pos 6
|
||
|
dimension 50
|
||
|
uid 123,0
|
||
|
)
|
||
|
*36 (MRCItem
|
||
|
litem &15
|
||
|
pos 7
|
||
|
dimension 80
|
||
|
uid 125,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 4
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 99,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 157,0
|
||
|
)
|
||
|
genericsCommonDM (CommonDM
|
||
|
ldm (LogicalDM
|
||
|
emptyRow *37 (LEmptyRow
|
||
|
)
|
||
|
uid 165,0
|
||
|
optionalChildren [
|
||
|
*38 (RefLabelRowHdr
|
||
|
)
|
||
|
*39 (TitleRowHdr
|
||
|
)
|
||
|
*40 (FilterRowHdr
|
||
|
)
|
||
|
*41 (RefLabelColHdr
|
||
|
tm "RefLabelColHdrMgr"
|
||
|
)
|
||
|
*42 (RowExpandColHdr
|
||
|
tm "RowExpandColHdrMgr"
|
||
|
)
|
||
|
*43 (GroupColHdr
|
||
|
tm "GroupColHdrMgr"
|
||
|
)
|
||
|
*44 (NameColHdr
|
||
|
tm "GenericNameColHdrMgr"
|
||
|
)
|
||
|
*45 (TypeColHdr
|
||
|
tm "GenericTypeColHdrMgr"
|
||
|
)
|
||
|
*46 (InitColHdr
|
||
|
tm "GenericValueColHdrMgr"
|
||
|
)
|
||
|
*47 (PragmaColHdr
|
||
|
tm "GenericPragmaColHdrMgr"
|
||
|
)
|
||
|
*48 (EolColHdr
|
||
|
tm "GenericEolColHdrMgr"
|
||
|
)
|
||
|
*49 (LogGeneric
|
||
|
generic (GiElement
|
||
|
name "bitNb"
|
||
|
type "positive"
|
||
|
value "32"
|
||
|
)
|
||
|
uid 155,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
pdm (PhysicalDM
|
||
|
uid 166,0
|
||
|
optionalChildren [
|
||
|
*50 (Sheet
|
||
|
sheetRow (SheetRow
|
||
|
headerVa (MVa
|
||
|
cellColor "49152,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
cellVa (MVa
|
||
|
cellColor "65535,65535,65535"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
groupVa (MVa
|
||
|
cellColor "39936,56832,65280"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
)
|
||
|
emptyMRCItem *51 (MRCItem
|
||
|
litem &37
|
||
|
pos 1
|
||
|
dimension 20
|
||
|
)
|
||
|
uid 131,0
|
||
|
optionalChildren [
|
||
|
*52 (MRCItem
|
||
|
litem &38
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 134,0
|
||
|
)
|
||
|
*53 (MRCItem
|
||
|
litem &39
|
||
|
pos 1
|
||
|
dimension 23
|
||
|
uid 136,0
|
||
|
)
|
||
|
*54 (MRCItem
|
||
|
litem &40
|
||
|
pos 2
|
||
|
hidden 1
|
||
|
dimension 20
|
||
|
uid 138,0
|
||
|
)
|
||
|
*55 (MRCItem
|
||
|
litem &49
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 156,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
sheetCol (SheetCol
|
||
|
propVa (MVa
|
||
|
cellColor "0,49152,49152"
|
||
|
fontColor "0,0,0"
|
||
|
font "Tahoma,10,0"
|
||
|
textAngle 90
|
||
|
)
|
||
|
uid 132,0
|
||
|
optionalChildren [
|
||
|
*56 (MRCItem
|
||
|
litem &41
|
||
|
pos 0
|
||
|
dimension 20
|
||
|
uid 140,0
|
||
|
)
|
||
|
*57 (MRCItem
|
||
|
litem &43
|
||
|
pos 1
|
||
|
dimension 50
|
||
|
uid 144,0
|
||
|
)
|
||
|
*58 (MRCItem
|
||
|
litem &44
|
||
|
pos 2
|
||
|
dimension 100
|
||
|
uid 146,0
|
||
|
)
|
||
|
*59 (MRCItem
|
||
|
litem &45
|
||
|
pos 3
|
||
|
dimension 100
|
||
|
uid 148,0
|
||
|
)
|
||
|
*60 (MRCItem
|
||
|
litem &46
|
||
|
pos 4
|
||
|
dimension 50
|
||
|
uid 150,0
|
||
|
)
|
||
|
*61 (MRCItem
|
||
|
litem &47
|
||
|
pos 5
|
||
|
dimension 50
|
||
|
uid 152,0
|
||
|
)
|
||
|
*62 (MRCItem
|
||
|
litem &48
|
||
|
pos 6
|
||
|
dimension 80
|
||
|
uid 154,0
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
fixedCol 3
|
||
|
fixedRow 2
|
||
|
name "Ports"
|
||
|
uid 130,0
|
||
|
vaOverrides [
|
||
|
]
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
uid 164,0
|
||
|
type 1
|
||
|
)
|
||
|
VExpander (VariableExpander
|
||
|
vvMap [
|
||
|
(vvPair
|
||
|
variable " "
|
||
|
value " "
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDLDir"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hdl"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "HDSDir"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataDesignDir"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallel@adder\\symbol.sb.info"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SideDataUserDir"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallel@adder\\symbol.sb.user"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "SourceDir"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "appl"
|
||
|
value "HDL Designer"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "arch_name"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "concat_file"
|
||
|
value "concatenated"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "config"
|
||
|
value "%(unit)_config"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallel@adder"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "d_logical"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallelAdder"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "date"
|
||
|
value "25.04.2012"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day"
|
||
|
value "mer."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "day_long"
|
||
|
value "mercredi"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "dd"
|
||
|
value "25"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "designName"
|
||
|
value "$DESIGN_NAME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "entity_name"
|
||
|
value "parallelAdder"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "ext"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_logical"
|
||
|
value "symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "f_noext"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "group"
|
||
|
value "UNKNOWN"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "host"
|
||
|
value "WE3673"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "language"
|
||
|
value "VHDL"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library"
|
||
|
value "pipelinedOperators"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_Generic_1_file"
|
||
|
value "U:\\SEm_curves\\Synthesis"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSim"
|
||
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_ModelSimCompiler"
|
||
|
value "$SCRATCH_DIR/SEm/pipelinedOperators/work"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "library_downstream_SpyGlass"
|
||
|
value "U:\\SEm_curves\\Synthesis"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "mm"
|
||
|
value "04"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "module_name"
|
||
|
value "parallelAdder"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month"
|
||
|
value "avr."
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "month_long"
|
||
|
value "avril"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallel@adder\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "p_logical"
|
||
|
value "C:\\Labs\\SEm_labs\\Prefs\\..\\pipelinedOperators\\hds\\parallelAdder\\symbol.sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "package_name"
|
||
|
value "<Undefined Variable>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "project_name"
|
||
|
value "hds-pipelinedOperators"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "series"
|
||
|
value "HDL Designer Series"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ADMS"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_DesignCompilerPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_HDSPath"
|
||
|
value "$HDS_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEBinPath"
|
||
|
value "$ISE_HOME"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ISEPath"
|
||
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_LeonardoPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_ModelSimPath"
|
||
|
value "$MODELSIM_HOME\\win32"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_NC"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_PrecisionRTLPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_QuestaSimPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "task_VCSPath"
|
||
|
value "<TBD>"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_ext"
|
||
|
value "sb"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "this_file_logical"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "time"
|
||
|
value "16:03:50"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "unit"
|
||
|
value "parallelAdder"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "user"
|
||
|
value "francois"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "version"
|
||
|
value "2009.2 (Build 10)"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "view"
|
||
|
value "symbol"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "year"
|
||
|
value "2012"
|
||
|
)
|
||
|
(vvPair
|
||
|
variable "yy"
|
||
|
value "12"
|
||
|
)
|
||
|
]
|
||
|
)
|
||
|
LanguageMgr "VhdlLangMgr"
|
||
|
uid 51,0
|
||
|
optionalChildren [
|
||
|
*63 (SymbolBody
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||
|
uid 8,0
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||
|
optionalChildren [
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||
|
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||
|
uid 57,0
|
||
|
ps "OnEdgeStrategy"
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|
shape (Triangle
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||
|
uid 82,0
|
||
|
ro 180
|
||
|
va (VaSet
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||
|
vasetType 1
|
||
|
fg "0,65535,0"
|
||
|
)
|
||
|
xt "39625,23000,40375,23750"
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||
|
)
|
||
|
tg (CPTG
|
||
|
uid 59,0
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||
|
ps "CptPortTextPlaceStrategy"
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||
|
stg "VerticalLayoutStrategy"
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||
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uid 60,0
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va (VaSet
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font "Verdana,9,0"
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st "sum"
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|
blo "39000,22800"
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|
tm "CptPortNameMgr"
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dt (MLText
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uid 61,0
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va (VaSet
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font "Courier New,8,0"
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|
thePort (LogicalPort
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||
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decl (Decl
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||
|
n "sum"
|
||
|
t "signed"
|
||
|
b "(bitNb-1 downto 0)"
|
||
|
o 1
|
||
|
suid 1,0
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||
|
)
|
||
|
)
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|
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|
*65 (CptPort
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|
uid 94,0
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||
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 95,0
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va (VaSet
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fg "0,65535,0"
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)
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tg (CPTG
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||
|
uid 96,0
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|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 97,0
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va (VaSet
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font "Verdana,9,0"
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st "cIn"
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|
ju 2
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||
|
blo "44334,19400"
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|
tm "CptPortNameMgr"
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dt (MLText
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uid 98,0
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va (VaSet
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font "Courier New,8,0"
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|
)
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|
thePort (LogicalPort
|
||
|
decl (Decl
|
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|
n "cIn"
|
||
|
t "std_ulogic"
|
||
|
o 2
|
||
|
suid 4,0
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|
)
|
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|
)
|
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|
)
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|
*66 (CptPort
|
||
|
uid 192,0
|
||
|
ps "OnEdgeStrategy"
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||
|
shape (Triangle
|
||
|
uid 237,0
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||
|
ro 270
|
||
|
va (VaSet
|
||
|
vasetType 1
|
||
|
fg "0,65535,0"
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|
)
|
||
|
xt "33917,18625,34667,19375"
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|
)
|
||
|
tg (CPTG
|
||
|
uid 194,0
|
||
|
ps "CptPortTextPlaceStrategy"
|
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|
stg "VerticalLayoutStrategy"
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|
f (Text
|
||
|
uid 195,0
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|
va (VaSet
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|
font "Verdana,9,0"
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)
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|
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|
st "cOut"
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|
blo "35667,19400"
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|
tm "CptPortNameMgr"
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)
|
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)
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dt (MLText
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uid 196,0
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va (VaSet
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font "Courier New,8,0"
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)
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st "cOut : OUT std_ulogic ;
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|
"
|
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|
)
|
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|
thePort (LogicalPort
|
||
|
m 1
|
||
|
decl (Decl
|
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|
n "cOut"
|
||
|
t "std_ulogic"
|
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|
o 3
|
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|
suid 2005,0
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|
)
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|
)
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|
)
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*67 (CptPort
|
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|
uid 199,0
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|
ps "OnEdgeStrategy"
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|
shape (Triangle
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uid 238,0
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|
ro 180
|
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|
va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
|
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uid 201,0
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|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 202,0
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va (VaSet
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ju 2
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blo "36300,16000"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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thePort (LogicalPort
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decl (Decl
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n "a"
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t "signed"
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b "(bitNb-1 downto 0)"
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o 4
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suid 2006,0
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)
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*68 (CptPort
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uid 204,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 205,0
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va (VaSet
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fg "0,65535,0"
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tg (CPTG
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uid 206,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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ju 2
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va (VaSet
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thePort (LogicalPort
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b "(bitNb-1 downto 0)"
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suid 2007,0
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uid 236,0
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va (VaSet
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stg "VerticalLayoutStrategy"
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)
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header "Generic Declarations"
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)
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|
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|
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|
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)
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portInstanceVis (PortSigDisplay
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blo "0,10800"
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externalLabel (Text
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va (VaSet
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xt "0,15000,2400,16000"
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st "User:"
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blo "0,15800"
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internalLabel (Text
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uid 6,0
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va (VaSet
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font "Arial,8,1"
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xt "0,9000,5800,10000"
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st "Internal User:"
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blo "0,9800"
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externalText (MLText
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uid 5,0
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va (VaSet
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tm "SyDeclarativeTextMgr"
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internalText (MLText
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uid 7,0
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va (VaSet
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font "Courier New,8,0"
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xt "0,9000,0,9000"
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tm "SyDeclarativeTextMgr"
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lastUid 261,0
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activeModelName "Symbol"
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)
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