49 lines
1.2 KiB
VHDL
49 lines
1.2 KiB
VHDL
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ARCHITECTURE RTL OF sdramControllerRefreshCounter IS
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signal delayCounter: unsigned(delayCounterBitNb-1 downto 0);
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signal endOfDelay: std_ulogic;
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BEGIN
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countDelay : process(reset, clock)
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begin
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if reset = '1' then
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delayCounter <= (others => '0');
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elsif rising_edge(clock) then
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if endOfDelay = '1' then
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delayCounter <= to_unsigned(1, delayCounter'length);
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else
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delayCounter <= delayCounter + 1;
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end if;
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end if;
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end process countDelay;
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findEndOfDelay: process(powerUpDone, delayCounter)
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begin
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endOfDelay <= '0';
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if powerUpDone = '0' then
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if delayCounter+1 = 0 then
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endOfDelay <= '1';
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end if;
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else
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if delayCounter+1 >= refreshPeriodNb then
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endOfDelay <= '1';
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end if;
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end if;
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end process findEndOfDelay;
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endOfRefreshCount <= endOfDelay;
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signalRefresh: process(powerUpDone, delayCounter)
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begin
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selectRefresh <= '0';
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if (powerUpDone = '1') and (delayCounter < 1024) then
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if (delayCounter <= 16) or (delayCounter(3 downto 0) = 0) then
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selectRefresh <= '1';
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end if;
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end if;
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end process signalRefresh;
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END ARCHITECTURE RTL;
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