58 lines
1.6 KiB
Tcl
58 lines
1.6 KiB
Tcl
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set board "arty-a7-35"
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# Create and clear output directory
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set outputdir work
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file mkdir $outputdir
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set files [glob -nocomplain "$outputdir/*"]
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if {[llength $files] != 0} {
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puts "deleting contents of $outputdir"
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file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
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} else {
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puts "$outputdir is empty"
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}
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switch $board {
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"arty-a7-35" {
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set a7part "xc7a35ticsg324-1L"
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set a7prj ${board}-test-setup
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}
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}
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# Create project
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create_project -part $a7part $a7prj $outputdir
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set_property board_part digilentinc.com:${board}:part0:1.0 [current_project]
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set_property target_language VHDL [current_project]
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# Define filesets
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## Core: NEORV32
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add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
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set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
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set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
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## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources
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set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd
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## Constraints
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set fileset_constraints [glob ./*.xdc]
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## Simulation-only sources
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set fileset_sim [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
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# Add source files
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## Design
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add_files $fileset_design
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## Constraints
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add_files -fileset constrs_1 $fileset_constraints
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## Simulation-only
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add_files -fileset sim_1 $fileset_sim
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# Run synthesis, implementation and bitstream generation
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launch_runs impl_1 -to_step write_bitstream -jobs 4
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wait_on_run impl_1
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