From 0233d8b730c6f4b0e4449e3d96368753888db0b2 Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 1 Mar 2024 14:53:57 +0100 Subject: [PATCH] split polygon in 2 process --- .../hdl/triangleToPolygon_studentVersion.vhd | 26 +- .../hds/waveform@gen/struct.bd.lck | 6 + .../hdl/waveformgen_tb_struct.vhg | 7 +- .../hdl/waveformgen_tester_entity.vhg | 3 +- .../hds/.xrf/waveformgen_tb_struct.xrf | 97 ++-- .../hds/.xrf/waveformgen_tester_entity.xrf | 21 +- .../hds/waveform@gen_tb/struct.bd | 371 +++++++++------ .../hds/waveform@gen_tb/struct.bd.bak | 11 +- .../hds/waveform@gen_tb/struct.bd.lck | 2 +- .../hds/waveform@gen_tester/interface | 433 ++++++++++-------- 10 files changed, 579 insertions(+), 398 deletions(-) create mode 100644 01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.lck diff --git a/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd b/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd index f88fdef..72e403b 100644 --- a/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd +++ b/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd @@ -2,26 +2,36 @@ ARCHITECTURE studentVersion OF triangleToPolygon IS signal mySignal : unsigned(bitNb downto 0); constant aFullTriangle : unsigned(bitNb downto 0) := (others => '1'); + signal bigTriangle: unsigned(bitNb downto 0); + signal oneOfHeight: unsigned(bitNb downto 0); + signal fiveOfHeight: unsigned(bitNb downto 0); BEGIN - convert: process(triangle) + resizeTriangle: process(triangle) + begin + bigTriangle <= ('0' & triangle) + ('0' & shift_right(triangle, 1)); + oneOfHeight <= shift_right(aFullTriangle, 3); + fiveOfHeight <= shift_right(aFullTriangle, 1) + shift_right(aFullTriangle, 3); + end process resizeTriangle; + + convert: process(bigTriangle) begin - if (('0' & triangle) + ('0' & shift_right(triangle, 1))) < shift_right(aFullTriangle, 3) then + if bigTriangle < oneOfHeight then - mySignal <= shift_right(aFullTriangle,3); + mySignal <= oneOfHeight; - elsif (('0' & triangle) + ('0' & shift_right(triangle, 1))) > (shift_right(aFullTriangle, 1) + shift_right('0' & aFullTriangle, 3)) then + elsif bigTriangle > fiveOfHeight then - mySignal <= (shift_right(aFullTriangle,1) + shift_right(aFullTriangle,3)); + mySignal <= fiveOfHeight; - elsif '1' then - mySignal <= ('0' & triangle) + ('0' & shift_right(triangle, 1) ); + else + mySignal <= bigTriangle; end if ; end process convert; - polygon <= resize(mySignal-shift_right('0' & aFullTriangle,3), bitNb); + polygon <= resize(mySignal-oneOfHeight, bitNb); END ARCHITECTURE studentVersion; diff --git a/01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.lck b/01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.lck new file mode 100644 index 0000000..71e5be3 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/waveform@gen/struct.bd.lck @@ -0,0 +1,6 @@ +EDIT_LOCK +remi.heredero +UNKNOWN +WE2330808 +15212 +01.03.2024-14:26:40.915000 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg index 4bf9eb9..7167441 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg +++ b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg @@ -3,7 +3,7 @@ -- -- Created: -- by - remi.heredero.UNKNOWN (WE2330808) --- at - 13:13:41 01.03.2024 +-- at - 14:26:40 01.03.2024 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) -- @@ -29,6 +29,7 @@ ARCHITECTURE struct OF waveformGen_tb IS SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0); SIGNAL reset : std_ulogic; SIGNAL sawtooth : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0); SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0); SIGNAL step : unsigned(bitNb-1 DOWNTO 0); SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0); @@ -62,6 +63,7 @@ ARCHITECTURE struct OF waveformGen_tb IS PORT ( polygon : IN unsigned (signalBitNb-1 DOWNTO 0); sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0); + sine : IN unsigned (signalBitNb-1 DOWNTO 0); square : IN unsigned (signalBitNb-1 DOWNTO 0); triangle : IN unsigned (signalBitNb-1 DOWNTO 0); clock : OUT std_ulogic ; @@ -93,7 +95,7 @@ BEGIN step => step, polygon => polygon, sawtooth => sawtooth, - sine => OPEN, + sine => sine, square => square, triangle => triangle ); @@ -105,6 +107,7 @@ BEGIN PORT MAP ( polygon => polygon, sawtooth => sawtooth, + sine => sine, square => square, triangle => triangle, clock => clock, diff --git a/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg index 8a39ba1..0d32e21 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg +++ b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg @@ -2,7 +2,7 @@ -- -- Created: -- by - remi.heredero.UNKNOWN (WE2330808) --- at - 13:12:24 01.03.2024 +-- at - 14:26:40 01.03.2024 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) -- @@ -20,6 +20,7 @@ ENTITY waveformGen_tester IS PORT( polygon : IN unsigned (signalBitNb-1 DOWNTO 0); sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0); + sine : IN unsigned (signalBitNb-1 DOWNTO 0); square : IN unsigned (signalBitNb-1 DOWNTO 0); triangle : IN unsigned (signalBitNb-1 DOWNTO 0); clock : OUT std_ulogic; diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf b/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf index 96a5b24..afd753d 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf @@ -33,136 +33,145 @@ VIEW struct.bd GRAPHIC 1180,0 30 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1263,0 31 0 +GRAPHIC 1404,0 31 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 594,0 32 0 +GRAPHIC 1263,0 32 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1308,0 33 0 +GRAPHIC 594,0 33 0 DESIGN waveform@gen_tb VIEW struct.bd -NO_GRAPHIC 34 +GRAPHIC 1308,0 34 0 DESIGN waveform@gen_tb VIEW struct.bd NO_GRAPHIC 35 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 36 LIBRARY WaveformGenerator DESIGN waveform@gen VIEW struct -GRAPHIC 954,0 37 0 +GRAPHIC 954,0 38 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 14,0 38 1 +GRAPHIC 14,0 39 1 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 52,0 43 0 +GRAPHIC 52,0 44 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 123,0 44 0 +GRAPHIC 123,0 45 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 88,0 45 0 +GRAPHIC 88,0 46 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 113,0 46 0 +GRAPHIC 113,0 47 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 93,0 47 0 +GRAPHIC 93,0 48 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 98,0 48 0 +GRAPHIC 98,0 49 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 103,0 49 0 +GRAPHIC 103,0 50 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 108,0 50 0 +GRAPHIC 108,0 51 0 DESIGN waveform@gen VIEW symbol.sb -GRAPHIC 118,0 51 0 +GRAPHIC 118,0 52 0 LIBRARY WaveformGenerator_test DESIGN waveform@gen_tester VIEW test -GRAPHIC 421,0 54 0 +GRAPHIC 421,0 55 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 14,0 55 1 +GRAPHIC 14,0 56 1 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1357,0 62 0 +GRAPHIC 1357,0 63 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1182,0 63 0 +GRAPHIC 1182,0 64 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1265,0 64 0 +GRAPHIC 1406,0 65 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1310,0 65 0 +GRAPHIC 1265,0 66 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 55,0 66 0 +GRAPHIC 1310,0 67 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 702,0 67 0 +GRAPHIC 55,0 68 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 47,0 68 0 +GRAPHIC 702,0 69 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 596,0 69 0 +GRAPHIC 47,0 70 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 596,0 71 0 LIBRARY WaveformGenerator_test DESIGN waveform@gen_tb VIEW struct.bd -NO_GRAPHIC 72 +NO_GRAPHIC 74 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 954,0 75 0 +GRAPHIC 954,0 77 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 421,0 76 0 -DESIGN waveform@gen_tb -VIEW struct.bd -NO_GRAPHIC 79 +GRAPHIC 421,0 78 0 DESIGN waveform@gen_tb VIEW struct.bd NO_GRAPHIC 81 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 954,0 83 0 +NO_GRAPHIC 83 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 961,0 84 1 +GRAPHIC 954,0 85 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 55,0 89 0 +GRAPHIC 961,0 86 1 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 702,0 90 0 +GRAPHIC 55,0 91 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 47,0 91 0 +GRAPHIC 702,0 92 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 596,0 92 0 +GRAPHIC 47,0 93 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1357,0 93 0 +GRAPHIC 596,0 94 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1182,0 94 0 +GRAPHIC 1357,0 95 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1265,0 96 0 +GRAPHIC 1182,0 96 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 1310,0 97 0 +GRAPHIC 1406,0 97 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 421,0 99 0 +GRAPHIC 1265,0 98 0 DESIGN waveform@gen_tb VIEW struct.bd -GRAPHIC 428,0 100 1 +GRAPHIC 1310,0 99 0 DESIGN waveform@gen_tb VIEW struct.bd -NO_GRAPHIC 115 +GRAPHIC 421,0 101 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 428,0 102 1 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 118 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf b/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf index 4dfebce..24b96b5 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf @@ -9,31 +9,34 @@ VIEW interface GRAPHIC 13,0 13 1 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1036,0 20 0 +GRAPHIC 1142,0 20 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1046,0 21 0 +GRAPHIC 1152,0 21 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1051,0 22 0 +GRAPHIC 1157,0 22 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1061,0 23 0 +GRAPHIC 1162,0 23 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1026,0 24 0 +GRAPHIC 1172,0 24 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1031,0 25 0 +GRAPHIC 1132,0 25 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1041,0 26 0 +GRAPHIC 1137,0 26 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1056,0 27 0 +GRAPHIC 1147,0 27 0 DESIGN waveform@gen_tester VIEW interface -GRAPHIC 1,0 30 0 +GRAPHIC 1167,0 28 0 DESIGN waveform@gen_tester VIEW interface GRAPHIC 1,0 31 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 1,0 32 0 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd index 63534b3..de32753 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd @@ -173,7 +173,7 @@ value "WE2330808" ) (vvPair variable "graphical_source_time" -value "13:13:41" +value "14:26:40" ) (vvPair variable "group" @@ -301,7 +301,7 @@ value "struct" ) (vvPair variable "time" -value "13:13:41" +value "14:26:40" ) (vvPair variable "unit" @@ -771,7 +771,7 @@ declText (MLText uid 595,0 va (VaSet ) -xt "2000,21800,29200,23000" +xt "2000,23000,29200,24200" st "SIGNAL step : unsigned(bitNb-1 DOWNTO 0) " ) @@ -1241,7 +1241,7 @@ declText (MLText uid 1264,0 va (VaSet ) -xt "2000,20600,32900,21800" +xt "2000,21800,32900,23000" st "SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0) " ) @@ -1259,7 +1259,7 @@ declText (MLText uid 1309,0 va (VaSet ) -xt "2000,23000,32700,24200" +xt "2000,24200,32700,25400" st "SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0) " ) @@ -1282,7 +1282,25 @@ st "SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0) " ) ) -*37 (Wire +*37 (Net +uid 1404,0 +decl (Decl +n "sine" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 13,0 +) +declText (MLText +uid 1405,0 +va (VaSet +) +xt "2000,20600,32200,21800" +st "SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0) +" +) +) +*38 (Wire uid 47,0 shape (OrthoPolyLine uid 48,0 @@ -1321,7 +1339,7 @@ tm "WireNameMgr" ) on &1 ) -*38 (Wire +*39 (Wire uid 55,0 shape (OrthoPolyLine uid 56,0 @@ -1360,7 +1378,7 @@ tm "WireNameMgr" ) on &2 ) -*39 (Wire +*40 (Wire uid 596,0 shape (OrthoPolyLine uid 597,0 @@ -1401,7 +1419,7 @@ tm "WireNameMgr" ) on &18 ) -*40 (Wire +*41 (Wire uid 702,0 shape (OrthoPolyLine uid 703,0 @@ -1440,7 +1458,7 @@ tm "WireNameMgr" ) on &19 ) -*41 (Wire +*42 (Wire uid 1182,0 shape (OrthoPolyLine uid 1183,0 @@ -1481,7 +1499,7 @@ tm "WireNameMgr" ) on &33 ) -*42 (Wire +*43 (Wire uid 1265,0 shape (OrthoPolyLine uid 1266,0 @@ -1522,7 +1540,7 @@ tm "WireNameMgr" ) on &34 ) -*43 (Wire +*44 (Wire uid 1310,0 shape (OrthoPolyLine uid 1311,0 @@ -1563,7 +1581,7 @@ tm "WireNameMgr" ) on &35 ) -*44 (Wire +*45 (Wire uid 1357,0 shape (OrthoPolyLine uid 1358,0 @@ -1604,6 +1622,47 @@ tm "WireNameMgr" ) on &36 ) +*46 (Wire +uid 1406,0 +shape (OrthoPolyLine +uid 1407,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "55750,26000,58000,38000" +pts [ +"55750,26000" +"58000,26000" +"58000,38000" +] +) +start &25 +end &14 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1410,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1411,0 +va (VaSet +font "Arial,12,0" +) +xt "57750,24500,60850,26000" +st "sine" +blo "57750,25700" +tm "WireNameMgr" +) +) +on &37 +) ] bg "65535,65535,65535" grid (Grid @@ -1616,11 +1675,11 @@ xShown 1 yShown 1 color "26368,26368,26368" ) -packageList *45 (PackageList +packageList *47 (PackageList uid 142,0 stg "VerticalLayoutStrategy" textVec [ -*46 (Text +*48 (Text uid 143,0 va (VaSet font "Arial,8,1" @@ -1629,7 +1688,7 @@ xt "0,0,6500,900" st "Package List" blo "0,700" ) -*47 (MLText +*49 (MLText uid 144,0 va (VaSet ) @@ -1645,7 +1704,7 @@ compDirBlock (MlTextGroup uid 145,0 stg "VerticalLayoutStrategy" textVec [ -*48 (Text +*50 (Text uid 146,0 va (VaSet isHidden 1 @@ -1655,7 +1714,7 @@ xt "20000,0,30000,900" st "Compiler Directives" blo "20000,700" ) -*49 (Text +*51 (Text uid 147,0 va (VaSet isHidden 1 @@ -1665,7 +1724,7 @@ xt "20000,1000,31500,1900" st "Pre-module directives:" blo "20000,1700" ) -*50 (MLText +*52 (MLText uid 148,0 va (VaSet isHidden 1 @@ -1675,7 +1734,7 @@ st "`resetall `timescale 1ns/10ps" tm "BdCompilerDirectivesTextMgr" ) -*51 (Text +*53 (Text uid 149,0 va (VaSet isHidden 1 @@ -1685,7 +1744,7 @@ xt "20000,4000,32000,4900" st "Post-module directives:" blo "20000,4700" ) -*52 (MLText +*54 (MLText uid 150,0 va (VaSet isHidden 1 @@ -1693,7 +1752,7 @@ isHidden 1 xt "20000,0,20000,0" tm "BdCompilerDirectivesTextMgr" ) -*53 (Text +*55 (Text uid 151,0 va (VaSet isHidden 1 @@ -1703,7 +1762,7 @@ xt "20000,5000,31500,5900" st "End-module directives:" blo "20000,5700" ) -*54 (MLText +*56 (MLText uid 152,0 va (VaSet isHidden 1 @@ -1714,7 +1773,7 @@ tm "BdCompilerDirectivesTextMgr" ] associable 1 ) -windowSize "0,0,1921,1056" +windowSize "0,24,1921,1080" viewArea "-1200,4500,107152,62100" cachedDiagramExtent "0,0,81000,55000" pageSetupInfo (PageSetupInfo @@ -1740,7 +1799,7 @@ boundaryWidth 0 ) hasePageBreakOrigin 1 pageBreakOrigin "0,0" -lastUid 1364,0 +lastUid 1413,0 defaultCommentText (CommentText shape (Rectangle layer 0 @@ -1827,7 +1886,7 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*55 (Text +*57 (Text va (VaSet font "Arial,9,0" ) @@ -1836,7 +1895,7 @@ st "" blo "1700,4200" tm "BdLibraryNameMgr" ) -*56 (Text +*58 (Text va (VaSet font "Arial,9,0" ) @@ -1845,7 +1904,7 @@ st "" blo "1700,5400" tm "BlkNameMgr" ) -*57 (Text +*59 (Text va (VaSet font "Arial,9,0" ) @@ -1883,21 +1942,21 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*58 (Text +*60 (Text va (VaSet ) xt "1000,3500,3300,4500" st "Library" blo "1000,4300" ) -*59 (Text +*61 (Text va (VaSet ) xt "1000,4500,7000,5500" st "MWComponent" blo "1000,5300" ) -*60 (Text +*62 (Text va (VaSet ) xt "1000,5500,1600,6500" @@ -1941,7 +2000,7 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*61 (Text +*63 (Text va (VaSet ) xt "1250,3500,3550,4500" @@ -1949,7 +2008,7 @@ st "Library" blo "1250,4300" tm "BdLibraryNameMgr" ) -*62 (Text +*64 (Text va (VaSet ) xt "1250,4500,6750,5500" @@ -1957,7 +2016,7 @@ st "SaComponent" blo "1250,5300" tm "CptNameMgr" ) -*63 (Text +*65 (Text va (VaSet ) xt "1250,5500,1850,6500" @@ -1995,21 +2054,21 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*64 (Text +*66 (Text va (VaSet ) xt "950,3500,3250,4500" st "Library" blo "950,4300" ) -*65 (Text +*67 (Text va (VaSet ) xt "950,4500,7050,5500" st "VhdlComponent" blo "950,5300" ) -*66 (Text +*68 (Text va (VaSet ) xt "950,5500,1550,6500" @@ -2049,21 +2108,21 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*67 (Text +*69 (Text va (VaSet ) xt "450,3500,2750,4500" st "Library" blo "450,4300" ) -*68 (Text +*70 (Text va (VaSet ) xt "450,4500,7550,5500" st "VerilogComponent" blo "450,5300" ) -*69 (Text +*71 (Text va (VaSet ) xt "450,5500,1050,6500" @@ -2101,7 +2160,7 @@ ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*70 (Text +*72 (Text va (VaSet ) xt "3400,4000,4600,5000" @@ -2109,7 +2168,7 @@ st "eb1" blo "3400,4800" tm "HdlTextNameMgr" ) -*71 (Text +*73 (Text va (VaSet ) xt "3400,5000,3800,6000" @@ -2506,7 +2565,7 @@ decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*72 (Text +*74 (Text va (VaSet font "Arial,8,1" ) @@ -2514,7 +2573,7 @@ xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) -*73 (MLText +*75 (MLText va (VaSet ) xt "14100,21000,14100,21000" @@ -2566,7 +2625,7 @@ decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ -*74 (Text +*76 (Text va (VaSet font "Arial,8,1" ) @@ -2574,7 +2633,7 @@ xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) -*75 (MLText +*77 (MLText va (VaSet ) xt "14100,21000,14100,21000" @@ -2685,8 +2744,7 @@ st "constant bitNb: positive := 16; constant signalBitNb: positive := 16; constant phaseBitNb: positive := 16; constant clockFrequency: real := 60.0E6; ---constant clockFrequency: real := 66.0E6; -" +--constant clockFrequency: real := 66.0E6;" tm "BdDeclarativeTextMgr" ) diagSignalLabel (Text @@ -2719,46 +2777,46 @@ tm "BdDeclarativeTextMgr" ) commonDM (CommonDM ldm (LogicalDM -suid 12,0 +suid 13,0 usingSuid 1 -emptyRow *76 (LEmptyRow +emptyRow *78 (LEmptyRow ) uid 717,0 optionalChildren [ -*77 (RefLabelRowHdr +*79 (RefLabelRowHdr ) -*78 (TitleRowHdr +*80 (TitleRowHdr ) -*79 (FilterRowHdr +*81 (FilterRowHdr ) -*80 (RefLabelColHdr +*82 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*81 (RowExpandColHdr +*83 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*82 (GroupColHdr +*84 (GroupColHdr tm "GroupColHdrMgr" ) -*83 (NameColHdr +*85 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*84 (ModeColHdr +*86 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*85 (TypeColHdr +*87 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*86 (BoundsColHdr +*88 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*87 (InitColHdr +*89 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*88 (EolColHdr +*90 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*89 (LeafLogPort +*91 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2770,7 +2828,7 @@ suid 1,0 ) uid 708,0 ) -*90 (LeafLogPort +*92 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2782,7 +2840,7 @@ suid 2,0 ) uid 710,0 ) -*91 (LeafLogPort +*93 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2795,7 +2853,7 @@ suid 3,0 ) uid 712,0 ) -*92 (LeafLogPort +*94 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2807,7 +2865,7 @@ suid 4,0 ) uid 714,0 ) -*93 (LeafLogPort +*95 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2820,7 +2878,7 @@ suid 5,0 ) uid 1188,0 ) -*94 (LeafLogPort +*96 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2833,7 +2891,7 @@ suid 10,0 ) uid 1271,0 ) -*95 (LeafLogPort +*97 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2846,7 +2904,7 @@ suid 11,0 ) uid 1316,0 ) -*96 (LeafLogPort +*98 (LeafLogPort port (LogicalPort m 4 decl (Decl @@ -2859,6 +2917,19 @@ suid 12,0 ) uid 1363,0 ) +*99 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "sine" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 13,0 +) +) +uid 1412,0 +) ] ) pdm (PhysicalDM @@ -2866,7 +2937,7 @@ displayShortBounds 1 editShortBounds 1 uid 730,0 optionalChildren [ -*97 (Sheet +*100 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" @@ -2883,80 +2954,86 @@ cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) -emptyMRCItem *98 (MRCItem -litem &76 -pos 8 +emptyMRCItem *101 (MRCItem +litem &78 +pos 9 dimension 20 ) uid 732,0 optionalChildren [ -*99 (MRCItem -litem &77 +*102 (MRCItem +litem &79 pos 0 dimension 20 uid 733,0 ) -*100 (MRCItem -litem &78 +*103 (MRCItem +litem &80 pos 1 dimension 23 uid 734,0 ) -*101 (MRCItem -litem &79 +*104 (MRCItem +litem &81 pos 2 hidden 1 dimension 20 uid 735,0 ) -*102 (MRCItem -litem &89 +*105 (MRCItem +litem &91 pos 0 dimension 20 uid 709,0 ) -*103 (MRCItem -litem &90 +*106 (MRCItem +litem &92 pos 1 dimension 20 uid 711,0 ) -*104 (MRCItem -litem &91 +*107 (MRCItem +litem &93 pos 2 dimension 20 uid 713,0 ) -*105 (MRCItem -litem &92 +*108 (MRCItem +litem &94 pos 3 dimension 20 uid 715,0 ) -*106 (MRCItem -litem &93 +*109 (MRCItem +litem &95 pos 4 dimension 20 uid 1189,0 ) -*107 (MRCItem -litem &94 +*110 (MRCItem +litem &96 pos 5 dimension 20 uid 1272,0 ) -*108 (MRCItem -litem &95 +*111 (MRCItem +litem &97 pos 6 dimension 20 uid 1317,0 ) -*109 (MRCItem -litem &96 +*112 (MRCItem +litem &98 pos 7 dimension 20 uid 1364,0 ) +*113 (MRCItem +litem &99 +pos 8 +dimension 20 +uid 1413,0 +) ] ) sheetCol (SheetCol @@ -2968,50 +3045,50 @@ textAngle 90 ) uid 736,0 optionalChildren [ -*110 (MRCItem -litem &80 +*114 (MRCItem +litem &82 pos 0 dimension 20 uid 737,0 ) -*111 (MRCItem -litem &82 +*115 (MRCItem +litem &84 pos 1 dimension 50 uid 738,0 ) -*112 (MRCItem -litem &83 +*116 (MRCItem +litem &85 pos 2 dimension 100 uid 739,0 ) -*113 (MRCItem -litem &84 +*117 (MRCItem +litem &86 pos 3 dimension 50 uid 740,0 ) -*114 (MRCItem -litem &85 +*118 (MRCItem +litem &87 pos 4 dimension 100 uid 741,0 ) -*115 (MRCItem -litem &86 +*119 (MRCItem +litem &88 pos 5 dimension 100 uid 742,0 ) -*116 (MRCItem -litem &87 +*120 (MRCItem +litem &89 pos 6 dimension 50 uid 743,0 ) -*117 (MRCItem -litem &88 +*121 (MRCItem +litem &90 pos 7 dimension 80 uid 744,0 @@ -3031,38 +3108,38 @@ uid 716,0 ) genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *118 (LEmptyRow +emptyRow *122 (LEmptyRow ) uid 746,0 optionalChildren [ -*119 (RefLabelRowHdr +*123 (RefLabelRowHdr ) -*120 (TitleRowHdr +*124 (TitleRowHdr ) -*121 (FilterRowHdr +*125 (FilterRowHdr ) -*122 (RefLabelColHdr +*126 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*123 (RowExpandColHdr +*127 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*124 (GroupColHdr +*128 (GroupColHdr tm "GroupColHdrMgr" ) -*125 (NameColHdr +*129 (NameColHdr tm "GenericNameColHdrMgr" ) -*126 (TypeColHdr +*130 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*127 (InitColHdr +*131 (InitColHdr tm "GenericValueColHdrMgr" ) -*128 (PragmaColHdr +*132 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*129 (EolColHdr +*133 (EolColHdr tm "GenericEolColHdrMgr" ) ] @@ -3070,7 +3147,7 @@ tm "GenericEolColHdrMgr" pdm (PhysicalDM uid 758,0 optionalChildren [ -*130 (Sheet +*134 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" @@ -3087,27 +3164,27 @@ cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) -emptyMRCItem *131 (MRCItem -litem &118 +emptyMRCItem *135 (MRCItem +litem &122 pos 0 dimension 20 ) uid 760,0 optionalChildren [ -*132 (MRCItem -litem &119 +*136 (MRCItem +litem &123 pos 0 dimension 20 uid 761,0 ) -*133 (MRCItem -litem &120 +*137 (MRCItem +litem &124 pos 1 dimension 23 uid 762,0 ) -*134 (MRCItem -litem &121 +*138 (MRCItem +litem &125 pos 2 hidden 1 dimension 20 @@ -3124,44 +3201,44 @@ textAngle 90 ) uid 764,0 optionalChildren [ -*135 (MRCItem -litem &122 +*139 (MRCItem +litem &126 pos 0 dimension 20 uid 765,0 ) -*136 (MRCItem -litem &124 +*140 (MRCItem +litem &128 pos 1 dimension 50 uid 766,0 ) -*137 (MRCItem -litem &125 +*141 (MRCItem +litem &129 pos 2 dimension 100 uid 767,0 ) -*138 (MRCItem -litem &126 +*142 (MRCItem +litem &130 pos 3 dimension 100 uid 768,0 ) -*139 (MRCItem -litem &127 +*143 (MRCItem +litem &131 pos 4 dimension 50 uid 769,0 ) -*140 (MRCItem -litem &128 +*144 (MRCItem +litem &132 pos 5 dimension 50 uid 770,0 ) -*141 (MRCItem -litem &129 +*145 (MRCItem +litem &133 pos 6 dimension 80 uid 771,0 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak index 2c71318..63534b3 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.bak @@ -173,7 +173,7 @@ value "WE2330808" ) (vvPair variable "graphical_source_time" -value "13:10:43" +value "13:13:41" ) (vvPair variable "group" @@ -301,7 +301,7 @@ value "struct" ) (vvPair variable "time" -value "13:10:43" +value "13:13:41" ) (vvPair variable "unit" @@ -740,8 +740,7 @@ va (VaSet ) xt "19000,50000,45200,52400" st "bitNb = bitNb ( positive ) -clockFrequency = clockFrequency ( real ) -" +clockFrequency = clockFrequency ( real ) " ) header "" ) @@ -2683,8 +2682,8 @@ va (VaSet ) xt "2000,7700,26900,13700" st "constant bitNb: positive := 16; -constant signalBit: positive := 16; -constant phaseBit: positive := 16; +constant signalBitNb: positive := 16; +constant phaseBitNb: positive := 16; constant clockFrequency: real := 60.0E6; --constant clockFrequency: real := 66.0E6; " diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck index fe67e30..fdddd37 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd.lck @@ -3,4 +3,4 @@ remi.heredero UNKNOWN WE2330808 15212 -01.03.2024-13:01:16.350000 +01.03.2024-14:26:32.427000 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface index e725094..17ed741 100644 --- a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tester/interface @@ -22,7 +22,7 @@ appVersion "2019.2 (Build 5)" model (Symbol commonDM (CommonDM ldm (LogicalDM -suid 84,0 +suid 93,0 usingSuid 1 emptyRow *1 (LEmptyRow ) @@ -68,10 +68,10 @@ decl (Decl n "clock" t "std_ulogic" o 1 -suid 77,0 +suid 85,0 ) ) -uid 1066,0 +uid 1177,0 ) *15 (LogPort port (LogicalPort @@ -80,10 +80,10 @@ decl (Decl n "en" t "std_ulogic" o 2 -suid 78,0 +suid 86,0 ) ) -uid 1068,0 +uid 1179,0 ) *16 (LogPort port (LogicalPort @@ -92,10 +92,10 @@ n "polygon" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 8 -suid 79,0 +suid 87,0 ) ) -uid 1070,0 +uid 1181,0 ) *17 (LogPort port (LogicalPort @@ -104,10 +104,10 @@ decl (Decl n "reset" t "std_ulogic" o 3 -suid 80,0 +suid 88,0 ) ) -uid 1072,0 +uid 1183,0 ) *18 (LogPort port (LogicalPort @@ -116,24 +116,36 @@ n "sawtooth" t "unsigned" b "(phaseBitNb-1 DOWNTO 0)" o 5 -suid 81,0 +suid 89,0 ) ) -uid 1074,0 +uid 1185,0 ) *19 (LogPort port (LogicalPort decl (Decl +n "sine" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 90,0 +) +) +uid 1187,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl n "square" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 6 -suid 82,0 +suid 91,0 ) ) -uid 1076,0 +uid 1189,0 ) -*20 (LogPort +*21 (LogPort port (LogicalPort m 1 decl (Decl @@ -141,22 +153,22 @@ n "step" t "unsigned" b "(bitNb-1 DOWNTO 0)" o 4 -suid 83,0 +suid 92,0 ) ) -uid 1078,0 +uid 1191,0 ) -*21 (LogPort +*22 (LogPort port (LogicalPort decl (Decl n "triangle" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 7 -suid 84,0 +suid 93,0 ) ) -uid 1080,0 +uid 1193,0 ) ] ) @@ -165,7 +177,7 @@ displayShortBounds 1 editShortBounds 1 uid 62,0 optionalChildren [ -*22 (Sheet +*23 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" @@ -182,79 +194,85 @@ cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) -emptyMRCItem *23 (MRCItem +emptyMRCItem *24 (MRCItem litem &1 pos 8 dimension 20 ) uid 64,0 optionalChildren [ -*24 (MRCItem +*25 (MRCItem litem &2 pos 0 dimension 20 uid 65,0 ) -*25 (MRCItem +*26 (MRCItem litem &3 pos 1 dimension 23 uid 66,0 ) -*26 (MRCItem +*27 (MRCItem litem &4 pos 2 hidden 1 dimension 20 uid 67,0 ) -*27 (MRCItem +*28 (MRCItem litem &14 pos 0 dimension 20 -uid 1067,0 +uid 1178,0 ) -*28 (MRCItem +*29 (MRCItem litem &15 pos 1 dimension 20 -uid 1069,0 +uid 1180,0 ) -*29 (MRCItem +*30 (MRCItem litem &16 pos 2 dimension 20 -uid 1071,0 +uid 1182,0 ) -*30 (MRCItem +*31 (MRCItem litem &17 pos 3 dimension 20 -uid 1073,0 +uid 1184,0 ) -*31 (MRCItem +*32 (MRCItem litem &18 pos 4 dimension 20 -uid 1075,0 +uid 1186,0 ) -*32 (MRCItem +*33 (MRCItem litem &19 pos 5 dimension 20 -uid 1077,0 +uid 1188,0 ) -*33 (MRCItem +*34 (MRCItem litem &20 pos 6 dimension 20 -uid 1079,0 +uid 1190,0 ) -*34 (MRCItem +*35 (MRCItem litem &21 pos 7 dimension 20 -uid 1081,0 +uid 1192,0 +) +*36 (MRCItem +litem &22 +pos 8 +dimension 20 +uid 1194,0 ) ] ) @@ -267,49 +285,49 @@ textAngle 90 ) uid 68,0 optionalChildren [ -*35 (MRCItem +*37 (MRCItem litem &5 pos 0 dimension 20 uid 69,0 ) -*36 (MRCItem +*38 (MRCItem litem &7 pos 1 dimension 50 uid 70,0 ) -*37 (MRCItem +*39 (MRCItem litem &8 pos 2 dimension 100 uid 71,0 ) -*38 (MRCItem +*40 (MRCItem litem &9 pos 3 dimension 50 uid 72,0 ) -*39 (MRCItem +*41 (MRCItem litem &10 pos 4 dimension 100 uid 73,0 ) -*40 (MRCItem +*42 (MRCItem litem &11 pos 5 dimension 100 uid 74,0 ) -*41 (MRCItem +*43 (MRCItem litem &12 pos 6 dimension 50 uid 75,0 ) -*42 (MRCItem +*44 (MRCItem litem &13 pos 7 dimension 80 @@ -330,41 +348,41 @@ uid 48,0 ) genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *43 (LEmptyRow +emptyRow *45 (LEmptyRow ) uid 78,0 optionalChildren [ -*44 (RefLabelRowHdr +*46 (RefLabelRowHdr ) -*45 (TitleRowHdr +*47 (TitleRowHdr ) -*46 (FilterRowHdr +*48 (FilterRowHdr ) -*47 (RefLabelColHdr +*49 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*48 (RowExpandColHdr +*50 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*49 (GroupColHdr +*51 (GroupColHdr tm "GroupColHdrMgr" ) -*50 (NameColHdr +*52 (NameColHdr tm "GenericNameColHdrMgr" ) -*51 (TypeColHdr +*53 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*52 (InitColHdr +*54 (InitColHdr tm "GenericValueColHdrMgr" ) -*53 (PragmaColHdr +*55 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*54 (EolColHdr +*56 (EolColHdr tm "GenericEolColHdrMgr" ) -*55 (LogGeneric +*57 (LogGeneric generic (GiElement name "bitNb" type "positive" @@ -372,7 +390,7 @@ value "16" ) uid 229,0 ) -*56 (LogGeneric +*58 (LogGeneric generic (GiElement name "clockFrequency" type "real" @@ -380,7 +398,7 @@ value "60.0E6" ) uid 611,0 ) -*57 (LogGeneric +*59 (LogGeneric generic (GiElement name "phaseBitNb" type "positive" @@ -388,7 +406,7 @@ value "16" ) uid 1105,0 ) -*58 (LogGeneric +*60 (LogGeneric generic (GiElement name "signalBitNb" type "positive" @@ -403,7 +421,7 @@ displayShortBounds 1 editShortBounds 1 uid 90,0 optionalChildren [ -*59 (Sheet +*61 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" @@ -420,52 +438,52 @@ cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) -emptyMRCItem *60 (MRCItem -litem &43 +emptyMRCItem *62 (MRCItem +litem &45 pos 4 dimension 20 ) uid 92,0 optionalChildren [ -*61 (MRCItem -litem &44 +*63 (MRCItem +litem &46 pos 0 dimension 20 uid 93,0 ) -*62 (MRCItem -litem &45 +*64 (MRCItem +litem &47 pos 1 dimension 23 uid 94,0 ) -*63 (MRCItem -litem &46 +*65 (MRCItem +litem &48 pos 2 hidden 1 dimension 20 uid 95,0 ) -*64 (MRCItem -litem &55 +*66 (MRCItem +litem &57 pos 0 dimension 20 uid 230,0 ) -*65 (MRCItem -litem &56 +*67 (MRCItem +litem &58 pos 1 dimension 20 uid 612,0 ) -*66 (MRCItem -litem &57 +*68 (MRCItem +litem &59 pos 2 dimension 20 uid 1106,0 ) -*67 (MRCItem -litem &58 +*69 (MRCItem +litem &60 pos 3 dimension 20 uid 1108,0 @@ -481,44 +499,44 @@ textAngle 90 ) uid 96,0 optionalChildren [ -*68 (MRCItem -litem &47 +*70 (MRCItem +litem &49 pos 0 dimension 20 uid 97,0 ) -*69 (MRCItem -litem &49 +*71 (MRCItem +litem &51 pos 1 dimension 50 uid 98,0 ) -*70 (MRCItem -litem &50 +*72 (MRCItem +litem &52 pos 2 dimension 100 uid 99,0 ) -*71 (MRCItem -litem &51 +*73 (MRCItem +litem &53 pos 3 dimension 100 uid 100,0 ) -*72 (MRCItem -litem &52 +*74 (MRCItem +litem &54 pos 4 dimension 50 uid 101,0 ) -*73 (MRCItem -litem &53 +*75 (MRCItem +litem &55 pos 5 dimension 50 uid 102,0 ) -*74 (MRCItem -litem &54 +*76 (MRCItem +litem &56 pos 6 dimension 80 uid 103,0 @@ -649,7 +667,7 @@ value "WE2330808" ) (vvPair variable "graphical_source_time" -value "13:12:24" +value "14:26:40" ) (vvPair variable "group" @@ -773,7 +791,7 @@ value "interface" ) (vvPair variable "time" -value "13:12:24" +value "14:26:40" ) (vvPair variable "unit" @@ -804,14 +822,14 @@ value "24" LanguageMgr "Vhdl2008LangMgr" uid 47,0 optionalChildren [ -*75 (SymbolBody +*77 (SymbolBody uid 8,0 optionalChildren [ -*76 (CptPort -uid 1026,0 +*78 (CptPort +uid 1132,0 ps "OnEdgeStrategy" shape (Triangle -uid 1027,0 +uid 1133,0 va (VaSet vasetType 1 fg "0,65535,0" @@ -819,11 +837,11 @@ fg "0,65535,0" xt "28625,5250,29375,6000" ) tg (CPTG -uid 1028,0 +uid 1134,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1029,0 +uid 1135,0 ro 270 va (VaSet font "Verdana,12,0" @@ -836,12 +854,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1030,0 +uid 1136,0 va (VaSet font "Courier New,8,0" ) -xt "44000,5200,61000,6000" -st "clock : OUT std_ulogic ;" +xt "44000,6000,61000,6800" +st "clock : OUT std_ulogic ; +" ) thePort (LogicalPort m 1 @@ -849,15 +868,15 @@ decl (Decl n "clock" t "std_ulogic" o 1 -suid 77,0 +suid 85,0 ) ) ) -*77 (CptPort -uid 1031,0 +*79 (CptPort +uid 1137,0 ps "OnEdgeStrategy" shape (Triangle -uid 1032,0 +uid 1138,0 va (VaSet vasetType 1 fg "0,65535,0" @@ -865,11 +884,11 @@ fg "0,65535,0" xt "26625,5250,27375,6000" ) tg (CPTG -uid 1033,0 +uid 1139,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1034,0 +uid 1140,0 ro 270 va (VaSet font "Verdana,12,0" @@ -882,12 +901,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1035,0 +uid 1141,0 va (VaSet font "Courier New,8,0" ) -xt "44000,6000,61000,6800" -st "en : OUT std_ulogic ;" +xt "44000,6800,61000,7600" +st "en : OUT std_ulogic ; +" ) thePort (LogicalPort m 1 @@ -895,15 +915,15 @@ decl (Decl n "en" t "std_ulogic" o 2 -suid 78,0 +suid 86,0 ) ) ) -*78 (CptPort -uid 1036,0 +*80 (CptPort +uid 1142,0 ps "OnEdgeStrategy" shape (Triangle -uid 1037,0 +uid 1143,0 ro 180 va (VaSet vasetType 1 @@ -912,11 +932,11 @@ fg "0,65535,0" xt "55625,5250,56375,6000" ) tg (CPTG -uid 1038,0 +uid 1144,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1039,0 +uid 1145,0 ro 270 va (VaSet font "Verdana,12,0" @@ -929,12 +949,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1040,0 +uid 1146,0 va (VaSet font "Courier New,8,0" ) xt "44000,2000,72500,2800" -st "polygon : IN unsigned (signalBitNb-1 DOWNTO 0) ;" +st "polygon : IN unsigned (signalBitNb-1 DOWNTO 0) ; +" ) thePort (LogicalPort decl (Decl @@ -942,15 +963,15 @@ n "polygon" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 8 -suid 79,0 +suid 87,0 ) ) ) -*79 (CptPort -uid 1041,0 +*81 (CptPort +uid 1147,0 ps "OnEdgeStrategy" shape (Triangle -uid 1042,0 +uid 1148,0 va (VaSet vasetType 1 fg "0,65535,0" @@ -958,11 +979,11 @@ fg "0,65535,0" xt "30625,5250,31375,6000" ) tg (CPTG -uid 1043,0 +uid 1149,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1044,0 +uid 1150,0 ro 270 va (VaSet font "Verdana,12,0" @@ -975,12 +996,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1045,0 +uid 1151,0 va (VaSet font "Courier New,8,0" ) -xt "44000,6800,61000,7600" -st "reset : OUT std_ulogic ;" +xt "44000,7600,61000,8400" +st "reset : OUT std_ulogic ; +" ) thePort (LogicalPort m 1 @@ -988,15 +1010,15 @@ decl (Decl n "reset" t "std_ulogic" o 3 -suid 80,0 +suid 88,0 ) ) ) -*80 (CptPort -uid 1046,0 +*82 (CptPort +uid 1152,0 ps "OnEdgeStrategy" shape (Triangle -uid 1047,0 +uid 1153,0 ro 180 va (VaSet vasetType 1 @@ -1005,11 +1027,11 @@ fg "0,65535,0" xt "63625,5250,64375,6000" ) tg (CPTG -uid 1048,0 +uid 1154,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1049,0 +uid 1155,0 ro 270 va (VaSet font "Verdana,12,0" @@ -1022,12 +1044,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1050,0 +uid 1156,0 va (VaSet font "Courier New,8,0" ) xt "44000,2800,72000,3600" -st "sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0) ;" +st "sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0) ; +" ) thePort (LogicalPort decl (Decl @@ -1035,15 +1058,63 @@ n "sawtooth" t "unsigned" b "(phaseBitNb-1 DOWNTO 0)" o 5 -suid 81,0 +suid 89,0 ) ) ) -*81 (CptPort -uid 1051,0 +*83 (CptPort +uid 1157,0 ps "OnEdgeStrategy" shape (Triangle -uid 1052,0 +uid 1158,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "53625,5250,54375,6000" +) +tg (CPTG +uid 1159,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1160,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "53300,7000,54700,10400" +st "sine" +ju 2 +blo "54500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1161,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,72500,4400" +st "sine : IN unsigned (signalBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "sine" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 90,0 +) +) +) +*84 (CptPort +uid 1162,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1163,0 ro 180 va (VaSet vasetType 1 @@ -1052,11 +1123,11 @@ fg "0,65535,0" xt "60625,5250,61375,6000" ) tg (CPTG -uid 1053,0 +uid 1164,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1054,0 +uid 1165,0 ro 270 va (VaSet font "Verdana,12,0" @@ -1069,12 +1140,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1055,0 +uid 1166,0 va (VaSet font "Courier New,8,0" ) -xt "44000,3600,72500,4400" -st "square : IN unsigned (signalBitNb-1 DOWNTO 0) ;" +xt "44000,4400,72500,5200" +st "square : IN unsigned (signalBitNb-1 DOWNTO 0) ; +" ) thePort (LogicalPort decl (Decl @@ -1082,15 +1154,15 @@ n "square" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 6 -suid 82,0 +suid 91,0 ) ) ) -*82 (CptPort -uid 1056,0 +*85 (CptPort +uid 1167,0 ps "OnEdgeStrategy" shape (Triangle -uid 1057,0 +uid 1168,0 va (VaSet vasetType 1 fg "0,65535,0" @@ -1098,11 +1170,11 @@ fg "0,65535,0" xt "22625,5250,23375,6000" ) tg (CPTG -uid 1058,0 +uid 1169,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1059,0 +uid 1170,0 ro 270 va (VaSet font "Verdana,12,0" @@ -1115,12 +1187,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1060,0 +uid 1171,0 va (VaSet font "Courier New,8,0" ) -xt "44000,7600,68500,8400" -st "step : OUT unsigned (bitNb-1 DOWNTO 0)" +xt "44000,8400,68500,9200" +st "step : OUT unsigned (bitNb-1 DOWNTO 0) +" ) thePort (LogicalPort m 1 @@ -1129,15 +1202,15 @@ n "step" t "unsigned" b "(bitNb-1 DOWNTO 0)" o 4 -suid 83,0 +suid 92,0 ) ) ) -*83 (CptPort -uid 1061,0 +*86 (CptPort +uid 1172,0 ps "OnEdgeStrategy" shape (Triangle -uid 1062,0 +uid 1173,0 ro 180 va (VaSet vasetType 1 @@ -1146,11 +1219,11 @@ fg "0,65535,0" xt "57625,5250,58375,6000" ) tg (CPTG -uid 1063,0 +uid 1174,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text -uid 1064,0 +uid 1175,0 ro 270 va (VaSet font "Verdana,12,0" @@ -1163,12 +1236,13 @@ tm "CptPortNameMgr" ) ) dt (MLText -uid 1065,0 +uid 1176,0 va (VaSet font "Courier New,8,0" ) -xt "44000,4400,72500,5200" -st "triangle : IN unsigned (signalBitNb-1 DOWNTO 0) ;" +xt "44000,5200,72500,6000" +st "triangle : IN unsigned (signalBitNb-1 DOWNTO 0) ; +" ) thePort (LogicalPort decl (Decl @@ -1176,7 +1250,7 @@ n "triangle" t "unsigned" b "(signalBitNb-1 DOWNTO 0)" o 7 -suid 84,0 +suid 93,0 ) ) ) @@ -1214,7 +1288,7 @@ st "waveformGen_tester" blo "35650,10800" ) ) -gi *84 (GenericInterface +gi *87 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" matrix (Matrix @@ -1230,8 +1304,7 @@ st "Generic Declarations bitNb positive 16 clockFrequency real 60.0E6 phaseBitNb positive 16 -signalBitNb positive 16 -" +signalBitNb positive 16 " ) header "Generic Declarations" showHdrWhenContentsEmpty 1 @@ -1281,11 +1354,11 @@ xShown 1 yShown 1 color "26368,26368,26368" ) -packageList *85 (PackageList +packageList *88 (PackageList uid 16,0 stg "VerticalLayoutStrategy" textVec [ -*86 (Text +*89 (Text uid 17,0 va (VaSet font "arial,8,1" @@ -1294,7 +1367,7 @@ xt "0,0,5400,1000" st "Package List" blo "0,800" ) -*87 (MLText +*90 (MLText uid 18,0 va (VaSet ) @@ -1421,7 +1494,7 @@ st "" blo "22200,16800" ) ) -gi *88 (GenericInterface +gi *91 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText @@ -1522,7 +1595,7 @@ o 0 ) ) ) -DeclarativeBlock *89 (SymDeclBlock +DeclarativeBlock *92 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text @@ -1548,9 +1621,9 @@ uid 4,0 va (VaSet font "Arial,8,1" ) -xt "42000,8400,44400,9400" +xt "42000,9200,44400,10200" st "User:" -blo "42000,9200" +blo "42000,10000" ) internalLabel (Text uid 6,0 @@ -1567,7 +1640,7 @@ uid 5,0 va (VaSet font "Courier New,8,0" ) -xt "44000,9400,44000,9400" +xt "44000,10200,44000,10200" tm "SyDeclarativeTextMgr" ) internalText (MLText @@ -1580,6 +1653,6 @@ xt "42000,0,42000,0" tm "SyDeclarativeTextMgr" ) ) -lastUid 1108,0 +lastUid 1194,0 activeModelName "Symbol:GEN" )