diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd index f21ae7a..20181ae 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd @@ -17,17 +17,46 @@ -- Read registers -- 00, data register provides the values detected on the lines. -- +signal addresses is unsigned(32 downto 0); +signal bRead is std_ulogic; +signal bWrite is std_ulogic; + ARCHITECTURE studentVersion OF ahbGpio IS BEGIN + process(hReset_n, hClk) begin + if hReset_n = '1' then + -- AHB-Lite + hRData <= (OTHERS => '0'); + hReady <= '0'; + hResp <= '0'; + + -- Out + ioOut <= (OTHERS => '0'); + ioEn <= (OTHERS => '0'); + + addresses <= (OTHERS => '0'); + bRead <= '0'; + bWrite <= '1'; + elsif rising_edge(hClk) then + if hSel = '1' then + CASE hAddr is + WHEN 00 => + WHEN 01 => + WHEN OTHERS + end CASE; + end if; + end if; + end process; + -- AHB-Lite - hRData <= (OTHERS => '0'); - hReady <= '0'; - hResp <= '0'; +-- hRData <= (OTHERS => '0'); +-- hReady <= '0'; +-- hResp <= '0'; -- Out - ioOut <= (OTHERS => '0'); - ioEn <= (OTHERS => '0'); +-- ioOut <= (OTHERS => '0'); +-- ioEn <= (OTHERS => '0'); END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbgpio_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbgpio_entity.vhg new file mode 100644 index 0000000..fe5d4fe --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbgpio_entity.vhg @@ -0,0 +1,38 @@ +-- VHDL Entity AhbLiteComponents.ahbGpio.symbol +-- +-- Created: +-- by - remi.heredero.UNKNOWN (WE2330808) +-- at - 15:08:33 23.02.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbGpio IS + GENERIC( + ioNb : positive := 8 + ); + PORT( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbGpio ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat new file mode 100644 index 0000000..00192e2 Binary files /dev/null and b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat differ diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbgpio_entity.xrf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbgpio_entity.xrf new file mode 100644 index 0000000..936d0d5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbgpio_entity.xrf @@ -0,0 +1,54 @@ +DESIGN ahb@gpio +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 104,0 8 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 13,0 15 1 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2452,0 19 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2514,0 20 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2519,0 21 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2692,0 22 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2494,0 23 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2464,0 24 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2474,0 25 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2839,0 26 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2469,0 27 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2504,0 28 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2509,0 29 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2846,0 30 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2651,0 31 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 1,0 34 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 1,0 35 0 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg new file mode 100644 index 0000000..a74e023 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity AhbLiteComponents_test.ahbGpio_tb.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:51:39 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY ahbGpio_tb IS +-- Declarations + +END ahbGpio_tb ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg new file mode 100644 index 0000000..b16008e --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg @@ -0,0 +1,148 @@ +-- +-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:06:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +LIBRARY AhbLiteComponents; +LIBRARY AhbLiteComponents_test; + +ARCHITECTURE struct OF ahbGpio_tb IS + + -- Architecture declarations + constant ioNb: positive := 8; + + constant clockFrequency : real := 60.0E6; + --constant clockFrequency : real := 66.0E6; + + -- Internal signal declarations + SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 ); + SIGNAL hClk : std_uLogic; + SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hReady : std_uLogic; + SIGNAL hReset_n : std_uLogic; + SIGNAL hResp : std_uLogic; + SIGNAL hSel : std_uLogic; + SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0); + SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hWrite : std_uLogic; + SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0); + SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0); + SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0); + SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT ahbGpio + GENERIC ( + ioNb : positive := 8 + ); + PORT ( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic ; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ahbGpio_tester + GENERIC ( + ioNb : positive; + clockFrequency : real + ); + PORT ( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : OUT std_uLogic ; + hReset_n : OUT std_uLogic ; + hSel : OUT std_uLogic ; + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic ; + io : INOUT std_logic_vector (ioNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio; + FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + tristate: process(ioEn, ioOut) + begin + for index in io'range loop + if ioEn(index) = '1' then + io(index) <= ioOut(index); + else + io(index) <= 'Z'; + end if; + end loop; + end process tristate; + + ioIn <= std_ulogic_vector(io); + + + -- Instance port mappings. + I_DUT : ahbGpio + GENERIC MAP ( + ioNb => ioNb + ) + PORT MAP ( + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSel, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + ioIn => ioIn, + hRData => hRData, + hReady => hReady, + hResp => hResp, + ioEn => ioEn, + ioOut => ioOut + ); + I_tester : ahbGpio_tester + GENERIC MAP ( + ioNb => ioNb, + clockFrequency => clockFrequency + ) + PORT MAP ( + hRData => hRData, + hReady => hReady, + hResp => hResp, + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSel, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + io => io + ); + +END struct; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg new file mode 100644 index 0000000..7477025 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg @@ -0,0 +1,37 @@ +-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:51:40 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbGpio_tester IS + GENERIC( + ioNb : positive; + clockFrequency : real + ); + PORT( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : OUT std_uLogic; + hReset_n : OUT std_uLogic; + hSel : OUT std_uLogic; + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic; + io : INOUT std_logic_vector (ioNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbGpio_tester ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat new file mode 100644 index 0000000..90746cf Binary files /dev/null and b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat differ diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf index 3eea781..376bb70 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf @@ -1 +1 @@ -DIALECT atom VHDL_ANY +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf index 3eea781..376bb70 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf @@ -1 +1 @@ -DIALECT atom VHDL_ANY +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_entity.xrf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_entity.xrf new file mode 100644 index 0000000..12d3fb8 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_entity.xrf @@ -0,0 +1,12 @@ +DESIGN ahb@gpio_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ahb@gpio_tb +VIEW symbol.sb +GRAPHIC 53,0 8 0 +DESIGN ahb@gpio_tb +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN ahb@gpio_tb +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_struct.xrf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_struct.xrf new file mode 100644 index 0000000..5ff1de6 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tb_struct.xrf @@ -0,0 +1,228 @@ +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 187,0 9 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 14 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 0,0 18 2 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 1,0 21 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 21 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12627,0 27 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12563,0 28 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12587,0 29 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12579,0 30 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12555,0 31 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12571,0 32 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12595,0 33 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12611,0 34 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12619,0 35 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12603,0 36 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13244,0 37 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13210,0 38 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13226,0 39 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13218,0 40 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 41 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 42 +LIBRARY AhbLiteComponents +DESIGN ahb@gpio +VIEW student@version +GRAPHIC 13194,0 44 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 14,0 45 1 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2452,0 49 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2514,0 50 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2519,0 51 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2692,0 52 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2494,0 53 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2464,0 54 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2474,0 55 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2839,0 56 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2469,0 57 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2504,0 58 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2509,0 59 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2846,0 60 0 +DESIGN ahb@gpio +VIEW symbol.sb +GRAPHIC 2651,0 61 0 +LIBRARY AhbLiteComponents_test +DESIGN ahb@gpio_tester +VIEW test +GRAPHIC 12657,0 64 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 14,0 65 1 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12589,0 70 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12581,0 71 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12573,0 72 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12629,0 73 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12565,0 74 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12557,0 75 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12597,0 76 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12613,0 77 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12621,0 78 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12605,0 79 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13236,0 80 0 +LIBRARY AhbLiteComponents_test +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 83 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13194,0 86 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12657,0 87 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 90 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13204,0 93 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 106 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 107 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13194,0 109 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13201,0 110 1 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12629,0 114 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12565,0 115 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12557,0 116 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12597,0 117 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12613,0 118 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12621,0 119 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12605,0 120 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13228,0 121 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12589,0 122 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12581,0 123 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12573,0 124 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13212,0 125 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 13220,0 126 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12657,0 128 0 +DESIGN ahb@gpio_tb +VIEW struct.bd +GRAPHIC 12664,0 129 1 +DESIGN ahb@gpio_tb +VIEW struct.bd +NO_GRAPHIC 147 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tester_entity.xrf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tester_entity.xrf new file mode 100644 index 0000000..f4d9c00 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbgpio_tester_entity.xrf @@ -0,0 +1,48 @@ +DESIGN ahb@gpio_tester +VIEW interface +NO_GRAPHIC 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 50,0 8 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 13,0 15 1 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 668,0 20 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 673,0 21 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 683,0 22 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 658,0 23 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 663,0 24 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 678,0 25 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 688,0 26 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 693,0 27 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 698,0 28 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 703,0 29 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 708,0 30 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 1,0 33 0 +DESIGN ahb@gpio_tester +VIEW interface +GRAPHIC 1,0 34 0 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.cache.dat b/06-07-08-09-SystemOnChip/Board/hds/.cache.dat new file mode 100644 index 0000000..a0fc07b Binary files /dev/null and b/06-07-08-09-SystemOnChip/Board/hds/.cache.dat differ diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs.bak b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs.bak new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs.bak @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs index 28c9b8f..44d6c07 100644 --- a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs @@ -1280,6 +1280,7 @@ projectPaths [ "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" +"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" ] libMappingsRootDir "" teamLibMappingsRootDir "" @@ -1300,288 +1301,144 @@ exportedDirectories [ exportStdIncludeRefs 1 exportStdPackageRefs 1 ) -printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN" +printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN" pageSizes [ (PageSizeInfo -name "12\" x 18\"" -type 512 -width 1106 -height 1658 +name "Letter" +width 783 +height 1013 ) (PageSizeInfo -name "11\" x 17\"" -type 17 -width 1013 -height 1566 -) -(PageSizeInfo -name "Legal (8,5\" x 14\")" +name "Legal" type 5 width 783 height 1290 ) (PageSizeInfo -name "Letter (8,5\" x 11\")" -width 783 -height 1013 -) -(PageSizeInfo -name "Executive (7,25\"x10,5\")" -type 7 -width 667 -height 967 -) -(PageSizeInfo -name "5,5\" x 8,5\"" +name "Statement" type 6 width 506 height 783 ) (PageSizeInfo -name "A3 (297 x 420 mm)" +name "Executive" +type 7 +width 667 +height 967 +) +(PageSizeInfo +name "A3" type 8 width 1077 height 1523 ) (PageSizeInfo -name "A4 (210 x 297 mm)" +name "A4" type 9 width 761 height 1077 ) (PageSizeInfo -name "A5 (148 x 210 mm)" +name "A5" type 11 -width 538 +width 536 height 761 ) (PageSizeInfo -name "A6 (105 x 148 mm)" -type 70 -width 380 -height 538 -) -(PageSizeInfo -name "B4 JIS (257 x 364 mm)" +name "B4 (JIS)" type 12 width 932 height 1320 ) (PageSizeInfo -name "B5 JIS (182 x 257 mm)" +name "B5 (JIS)" type 13 width 660 height 932 ) (PageSizeInfo -name "B6 JIS (128 x 182 mm)" -type 88 -width 464 -height 660 +name "11×17" +type 17 +width 1013 +height 1566 ) (PageSizeInfo -name "8\" x 13\"" -type 518 -width 737 -height 1198 -) -(PageSizeInfo -name "8,25\" x 13\"" -type 519 -width 760 -height 1198 -) -(PageSizeInfo -name "8,5\" x 13\"" -type 14 -width 783 -height 1198 -) -(PageSizeInfo -name "8.5\" x 13.4\"" -type 551 -width 783 -height 1235 -) -(PageSizeInfo -name "Com10 Env.(4,125\"x9,5\")" +name "Envelope #10" type 20 -width 380 +width 379 height 875 ) (PageSizeInfo -name "Env.Monar.(3,875\"x7,5\")" -type 37 -width 357 -height 691 -) -(PageSizeInfo -name "Env. DL (110 x 220 mm)" +name "Envelope DL" type 27 width 399 height 798 ) (PageSizeInfo -name "Env. C6 (114 x 162 mm)" -type 31 -width 413 -height 587 -) -(PageSizeInfo -name "Env. C5 (162 x 229 mm)" +name "Envelope C5" type 28 width 587 height 830 ) (PageSizeInfo -name "8K (267 x 390 mm)" -type 520 -width 968 -height 1415 +name "Envelope B5" +type 34 +width 638 +height 907 ) (PageSizeInfo -name "16K (195 x 267 mm)" -type 521 -width 707 -height 968 +name "Envelope Monarch" +type 37 +width 357 +height 691 ) (PageSizeInfo -name "8,25\" x 14\"" -type 522 -width 760 -height 1290 +name "Japanese Postcard" +type 43 +width 362 +height 536 ) (PageSizeInfo -name "11\" x 14\"" -type 524 -width 1013 -height 1290 +name "A6" +type 70 +width 380 +height 536 ) (PageSizeInfo -name "13\" x 19,2\"" -type 525 -width 1198 -height 1769 +name "Double Japan Postcard Rotated" +type 82 +width 536 +height 725 ) (PageSizeInfo -name "13\" x 19\"" -type 526 -width 1198 -height 1751 +name "Executive (JIS)" +type 119 +width 783 +height 1196 ) (PageSizeInfo -name "12,6\" x 19,2\"" -type 527 -width 1161 -height 1769 +name "Oficio 8.5x13" +type 120 +width 783 +height 1198 ) (PageSizeInfo -name "12,6\" x 18,5\"" -type 528 -width 1161 -height 1704 -) -(PageSizeInfo -name "13\" x 18\"" -type 529 -width 1198 +name "12x18" +type 121 +width 1105 height 1658 ) (PageSizeInfo -name "10\" x 14\"" -type 16 -width 921 -height 1290 +name "8K 273x394 mm" +type 139 +width 990 +height 1428 ) (PageSizeInfo -name "10\" x 15\"" -type 546 -width 921 -height 1382 -) -(PageSizeInfo -name "11\" x 15\"" -type 539 -width 1013 -height 1382 -) -(PageSizeInfo -name "SRA3 (320 x 450 mm)" -type 530 -width 1161 -height 1632 -) -(PageSizeInfo -name "SRA4 (225 x 320 mm)" -type 531 -width 816 -height 1161 -) -(PageSizeInfo -name "Format papier personnalisé" -type 256 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size1(215,9 x 279,4 mm)" -type 257 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size2(215,9 x 279,4 mm)" -type 258 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size3(215,9 x 279,4 mm)" -type 259 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size4(215,9 x 279,4 mm)" -type 260 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size5(215,9 x 279,4 mm)" -type 261 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size6(215,9 x 279,4 mm)" -type 262 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size7(215,9 x 279,4 mm)" -type 263 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size8(215,9 x 279,4 mm)" -type 264 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size9(215,9 x 279,4 mm)" -type 265 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size10(215,9 x 279,4 mm)" -type 266 -width 783 -height 1013 +name "16K 197x273 mm" +type 140 +width 714 +height 990 ) ] exportPageSetupInfo (PageSetupInfo @@ -4292,7 +4149,7 @@ hdsWorkspaceLocation "" relativeLibraryRootDir "" vmLabelLatestDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0 -logWindowGeometry "636x406+-823+276" +logWindowGeometry "636x406+308+98" diagramBrowserTabNo 0 showInsertPortHint 0 showContentFirstTime 0 @@ -6384,11 +6241,11 @@ size 180 ] displayHierarchy 0 xPos 0 -yPos 0 -width 1936 -height 1056 +yPos 9 +width 974 +height 1047 activeSidePanelTab 2 -activeLibraryTab 1 +activeLibraryTab 5 sidePanelSize 278 showUnixHiddenFiles 0 componentBrowserXpos 569 diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak new file mode 100644 index 0000000..28c9b8f --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak @@ -0,0 +1,6866 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "qws" +Description "Quartus Workspace" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "args" +Description "Quartus Arguments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rpt" +Description "Quartus Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "summary" +Description "Quartus Summary File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "eqn" +Description "Quartus Equation File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pin" +Description "Quartus Pin Information File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "vqm" +Description "Quartus Verilog Mapping File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\vqm.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdo" +Description "Standard Delay File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "csv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ppt" +Description "Microsoft PowerPoint Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\powerpoint.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "vsd" 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+gridVisible 0 +gridSnapping 0 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +visibilityPrefs [ +(StringToBool +display "Architecture Declarations (VHDL)" +status 1 +) +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Concurrent Statements" +status 1 +) +(StringToBool +display "Global Actions" +status 1 +) +(StringToBool +display "Module Declarations (Verilog)" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +(StringToBool +display "Process Declarations (VHDL)" +status 1 +) +(StringToBool +display "Signal Status" +status 1 +) +(StringToBool +display "State Register Statements" +status 1 +) +] +clockNameVaSet (VaSet +) +clockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +resetNameVaSet (VaSet +) +resetShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +enableNameVaSet (VaSet +) +enableShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +ccondNameVaSet (VaSet +) +ccondShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +recoveryShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +stateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +stateNameVaSet (VaSet +font "Verdana,12,1" +) +stateEncodingVaSet (VaSet +font "Verdana,9,1" +) +stateActionsVaSet (VaSet +) +stateActionShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +stateCaseVaSet (VaSet +font "Verdana,9,1" +) +cStateShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "0,0,32768" +lineWidth 2 +) +cStateNameVaSet (VaSet +font "Verdana,10,1" +) +junctionShapeVaSet (VaSet +vasetType 1 +fg "59904,39936,65280" +) +junctionNameVaSet (VaSet +font "Verdana,9,1" +) +junctionSymbolVaSet (VaSet +font "Verdana,10,1" +) +entryPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) +interruptPointShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +linkShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +linkNameVaSet (VaSet +font "Verdana,9,1" +) +exitPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) +wStateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "26368,26368,26368" +lineWidth 2 +) +wStateTextVaSet (VaSet +fg "0,0,32768" +font "Verdana,12,1" +) +tBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +) +tBlockActionsVaSet (VaSet +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +localDeclValueVaSet (VaSet +font "Courier New,8,0" +) +processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk index ba578c2..e700175 100644 --- a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -46,7 +46,7 @@ settingsMap [ "GlitchGeneration" "1" "InitCmd" -"$SIMULATION_DIR/beamerSoc.do" +"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbGpio.do" "LogFile" "" "RemoteHost" diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.cache.dat b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.cache.dat new file mode 100644 index 0000000..dc8a179 Binary files /dev/null and b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.cache.dat differ diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.cache.dat b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.cache.dat new file mode 100644 index 0000000..1ff33df Binary files /dev/null and b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.cache.dat differ diff --git a/Libs/AhbLite/hds/.cache.dat b/Libs/AhbLite/hds/.cache.dat new file mode 100644 index 0000000..a6b4317 Binary files /dev/null and b/Libs/AhbLite/hds/.cache.dat differ diff --git a/Libs/Lattice/hds/.cache.dat b/Libs/Lattice/hds/.cache.dat index 246f86e..5e0c4b9 100644 Binary files a/Libs/Lattice/hds/.cache.dat and b/Libs/Lattice/hds/.cache.dat differ diff --git a/Libs/NanoBlaze/hds/.cache.dat b/Libs/NanoBlaze/hds/.cache.dat new file mode 100644 index 0000000..ff600d3 Binary files /dev/null and b/Libs/NanoBlaze/hds/.cache.dat differ