From 536477d656d4779af3c25f3ae2e96fe80c29617c Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 3 May 2024 15:02:20 +0200 Subject: [PATCH] some file i don't know if needed --- .../AhbLiteComponents/hdl/ahbuart_entity.vhg | 38 ++++ .../AhbLiteComponents/hds/.cache.dat | Bin 1270 -> 1378 bytes .../hds/.xrf/ahbuart_entity.xrf | 51 +++++ .../hdl/ahbuart_tb_entity.vhg | 15 ++ .../hdl/ahbuart_tb_struct.vhg | 132 +++++++++++ .../hdl/ahbuart_tester_entity.vhg | 37 +++ .../AhbLiteComponents_test/hds/.cache.dat | Bin 5134 -> 5471 bytes .../hds/.xrf/ahbuart_tb_entity.xrf | 12 + .../hds/.xrf/ahbuart_tb_struct.xrf | 213 ++++++++++++++++++ .../hds/.xrf/ahbuart_tester_entity.xrf | 51 +++++ .../Prefs/hds_user/v2019.2/hds_user_prefs.bak | 3 +- .../v2019.2/tasks/modelsim_simulate.tsk | 2 +- 12 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_entity.xrf create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_struct.xrf create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tester_entity.xrf diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg new file mode 100644 index 0000000..15c7f47 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg @@ -0,0 +1,38 @@ +-- VHDL Entity AhbLiteComponents.ahbUart.symbol +-- +-- Created: +-- by - remi.heredero.UNKNOWN (WE2330808) +-- at - 15:08:33 23.02.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbUart IS + GENERIC( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT( + RxD : IN std_ulogic; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + TxD : OUT std_ulogic; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic + ); + +-- Declarations + +END ahbUart ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat index 7bcdd9199fb4d9e299fb80fc1f83baca993ffe5c..1092b6bcae2343713ad792bfa191254807a11f1c 100644 GIT binary patch delta 66 zcmeyy`G{*mAS2txpjbwx>e|U08NC&R6El)Z6N^gXQ}aqPODgrsGSV49AWgky0Rsa| U`eaAOfK5z>OpL6PjaZHV0Ns-l`v3p{ delta 30 mcmaFF^^J2vAS3I>pjbwxs-(#q8ND}WFqtwjvP_=Gas&XP!3p#L diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf new file mode 100644 index 0000000..868d879 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf @@ -0,0 +1,51 @@ +DESIGN ahb@uart +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 104,0 8 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 13,0 15 1 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2839,0 20 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2452,0 21 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2514,0 22 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2519,0 23 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2692,0 24 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2494,0 25 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2464,0 26 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2474,0 27 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2651,0 28 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2469,0 29 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2504,0 30 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 2509,0 31 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 1,0 34 0 +DESIGN ahb@uart +VIEW symbol.sb +GRAPHIC 1,0 35 0 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg new file mode 100644 index 0000000..6df248a --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol +-- +-- Created: +-- by - zas.UNKNOWN (ZELL) +-- at - 17:08:42 02/17/2020 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY ahbUart_tb IS +-- Declarations + +END ahbUart_tb ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg new file mode 100644 index 0000000..21c9f7b --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg @@ -0,0 +1,132 @@ +-- +-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:07:00 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +LIBRARY AhbLiteComponents; +LIBRARY AhbLiteComponents_test; + +ARCHITECTURE struct OF ahbUart_tb IS + + -- Architecture declarations + constant txFifoDepth: positive := 1; + constant rxFifoDepth: positive := 1; + + constant clockFrequency : real := 60.0E6; + --constant clockFrequency : real := 66.0E6; + + -- Internal signal declarations + SIGNAL RxD : std_ulogic; + SIGNAL TxD : std_ulogic; + SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 ); + SIGNAL hClk : std_uLogic; + SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hReady : std_uLogic; + SIGNAL hReset_n : std_uLogic; + SIGNAL hResp : std_uLogic; + SIGNAL hSel : std_uLogic; + SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0); + SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hWrite : std_uLogic; + + + -- Component Declarations + COMPONENT ahbUart + GENERIC ( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT ( + RxD : IN std_ulogic ; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + TxD : OUT std_ulogic ; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbUart_tester + GENERIC ( + clockFrequency : real + ); + PORT ( + TxD : IN std_ulogic ; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + RxD : OUT std_ulogic ; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : OUT std_uLogic ; + hReset_n : OUT std_uLogic ; + hSel : OUT std_uLogic ; + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart; + FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_DUT : ahbUart + GENERIC MAP ( + txFifoDepth => txFifoDepth, + rxFifoDepth => rxFifoDepth + ) + PORT MAP ( + RxD => RxD, + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSel, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + TxD => TxD, + hRData => hRData, + hReady => hReady, + hResp => hResp + ); + I_tester : ahbUart_tester + GENERIC MAP ( + clockFrequency => clockFrequency + ) + PORT MAP ( + TxD => TxD, + hRData => hRData, + hReady => hReady, + hResp => hResp, + RxD => RxD, + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSel, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite + ); + +END struct; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg new file mode 100644 index 0000000..212a358 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg @@ -0,0 +1,37 @@ +-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface +-- +-- Created: +-- by - zas.UNKNOWN (ZELL) +-- at - 17:08:42 02/17/2020 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbUart_tester IS + GENERIC( + clockFrequency : real + ); + PORT( + TxD : IN std_ulogic; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + RxD : OUT std_ulogic; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : OUT std_uLogic; + hReset_n : OUT std_uLogic; + hSel : OUT std_uLogic; + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic + ); + +-- Declarations + +END ahbUart_tester ; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat index 5180cf8fdc4402b6b71f2b72a2e58778057fd292..44223d3ebe79fbffab56b539b4c74eec21c2ed3e 100644 GIT binary patch delta 202 zcmeCvxUV%Kj8SA`co@s%4@@lbrHMr)@g+&|sd*)tC6#(*8R-l_z@4UE^MiqbQE9R; za{ydTaY<2WatWFmfk>blA9bn3j3kIzsl_F!MQG+RK+I$DocxtJVDmY zPVV5$WfTCiW=y^y$jvASWKGV9$3QhJET)-&2 J`JJEw69B?AKnwr? delta 77 zcmV-T0J8tzDvl_SRsj*QS5^eG{spB30SuA~HIvy2Z2=9E3Ye4M3k#E@5H_