From 6ce04fe6d43ce8f81298075adea6279da37cb5cc Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 19 Apr 2024 16:11:36 +0200 Subject: [PATCH] add ahbGPIO --- .../hdl/ahbGpio_studentVersion.vhd | 102 +- .../AhbLiteComponents/hds/.cache.dat | Bin 1270 -> 1270 bytes .../hdl/ahbgpio_tb_struct.vhg | 4 +- .../AhbLiteComponents_test/hds/.cache.dat | Bin 5134 -> 5134 bytes .../hds/ahb@gpio_tb/struct.bd | 88 +- .../hds/ahb@gpio_tb/struct.bd.bak | 4005 +++++++++++++++++ .../Prefs/hds_user/v2019.2/hds_user_prefs | 93 +- .../Prefs/hds_user/v2019.2/hds_user_prefs.bak | 375 +- 8 files changed, 4387 insertions(+), 280 deletions(-) create mode 100644 06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd.bak diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd index 20181ae..37e0f2c 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd @@ -17,18 +17,22 @@ -- Read registers -- 00, data register provides the values detected on the lines. -- -signal addresses is unsigned(32 downto 0); -signal bRead is std_ulogic; -signal bWrite is std_ulogic; - ARCHITECTURE studentVersion OF ahbGpio IS + +signal addresses: unsigned(hAddr'range); +signal bRead: std_ulogic; +signal bWrite: std_ulogic; +signal bDone: std_ulogic; + + BEGIN process(hReset_n, hClk) begin - if hReset_n = '1' then + if hReset_n = '0' then -- AHB-Lite + --hRData <= (OTHERS => 'Z'); hRData <= (OTHERS => '0'); - hReady <= '0'; + hReady <= '1'; hResp <= '0'; -- Out @@ -37,16 +41,90 @@ BEGIN addresses <= (OTHERS => '0'); bRead <= '0'; - bWrite <= '1'; + bWrite <= '0'; + bDone <= '0'; elsif rising_edge(hClk) then if hSel = '1' then - CASE hAddr is - WHEN 00 => - WHEN 01 => - WHEN OTHERS - end CASE; + bWrite <= hWrite; + bRead <= not hWrite; + addresses <= hAddr; + hReady <= '0'; + bDone <= '0'; + else + bWrite <= '0'; + bRead <= '0'; end if; + + if bRead = '1' and bWrite = '0' then + ------------------------------------------------------------------------- + -- READ + ------------------------------------------------------------------------- + + if addresses = "00" then + -- ##### Read data register ##### + --hRData <= unsigned(resize(ioIn, ioNb)); + for i in 0 to ioNb-1 loop + hRData(i) <= ioIn(i); + end loop; + bDone <= '1'; + + elsif addresses = "01" then + report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error; + + end if; + + elsif bRead = '0' and bWrite = '1' then + ------------------------------------------------------------------------- + -- WRITE + ------------------------------------------------------------------------- + + if addresses = "00" then + -- ##### Write data register ##### + --ioOut <= resize(std_ulogic_vector(hWData), ioNb); + for i in 0 to ioNb-1 loop + ioOut(i) <= hWData(i); + end loop; + bDone <= '1'; + + elsif addresses = "01" then + -- ##### Write direction register ##### + --ioEn <= hWData; + for i in 0 to ioNb-1 loop + ioEn(i) <= hWData(i); + end loop; + bDone <= '1'; + + end if; + + elsif bRead = '1' and bWrite = '1' then + ------------------------------------------------------------------------- + -- SHOULD NEVER HAPPEN + ------------------------------------------------------------------------- + report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error; + + end if; + + if (ioIn and ioEn) = (ioEn and ioOut) then + hResp <= '0'; + else + hResp <= '1'; + end if; + + if bDone = '1' then + --hRData <= (OTHERS => 'Z'); + bDone <= '0'; + hReady <= '1'; + end if; + end if; + + for i in (ioNb-1) downto 0 loop + if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then + --ioEn(i) <= '0'; + report "an output was in conflict" severity note; + end if; + end loop; + end process; -- AHB-Lite diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat index 00192e23befb9fc1a1e9bd69b3fe950246da0327..7bcdd9199fb4d9e299fb80fc1f83baca993ffe5c 100644 GIT binary patch delta 20 bcmeyy`HgeKI!1P-sw4&m{+7*K86BAcP<;lY delta 20 ccmeyy`HgeKI!1Q+En68FSba8cWprc)091bl>i_@% diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg index b16008e..c51d947 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg @@ -2,8 +2,8 @@ -- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct -- -- Created: --- by - axel.amand.UNKNOWN (WE7860) --- at - 15:06:49 28.04.2023 +-- by - remi.heredero.UNKNOWN (WE2330808) +-- at - 14:16:25 19.04.2024 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) -- diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat index 90746cf30f31a043c30a43a5088d0e5390bfaaa1..5180cf8fdc4402b6b71f2b72a2e58778057fd292 100644 GIT binary patch delta 46 zcmeCv=+l@`$&sd%Fq47ds>sI1Urg*uRmlttLNg}|Gy7~l$9#y71thz9icl3J0Bp+- AX#fBK delta 45 zcmV+|0Mh@CD2^zQc?f0Lrr`hp)4Q>O`T_?Zv=jgU5|fh?15C5d1HulI3=<2pn-X&Y Dn}QH) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd index 018b5fa..67e961c 100644 --- a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd @@ -74,23 +74,23 @@ value " " ) (vvPair variable "HDLDir" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" ) (vvPair variable "HDSDir" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" ) (vvPair variable "SideDataDesignDir" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" ) (vvPair variable "SideDataUserDir" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" ) (vvPair variable "SourceDir" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" ) (vvPair variable "appl" @@ -114,15 +114,15 @@ value "%(unit)_%(view)_config" ) (vvPair variable "d" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" ) (vvPair variable "d_logical" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb" ) (vvPair variable "date" -value "28.04.2023" +value "19.04.2024" ) (vvPair variable "day" @@ -134,7 +134,7 @@ value "vendredi" ) (vvPair variable "dd" -value "28" +value "19" ) (vvPair variable "designName" @@ -162,11 +162,11 @@ value "struct" ) (vvPair variable "graphical_source_author" -value "axel.amand" +value "remi.heredero" ) (vvPair variable "graphical_source_date" -value "28.04.2023" +value "19.04.2024" ) (vvPair variable "graphical_source_group" @@ -174,11 +174,11 @@ value "UNKNOWN" ) (vvPair variable "graphical_source_host" -value "WE7860" +value "WE2330808" ) (vvPair variable "graphical_source_time" -value "15:06:49" +value "14:16:25" ) (vvPair variable "group" @@ -186,7 +186,7 @@ value "UNKNOWN" ) (vvPair variable "host" -value "WE7860" +value "WE2330808" ) (vvPair variable "language" @@ -222,11 +222,11 @@ value "avril" ) (vvPair variable "p" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd" ) (vvPair variable "p_logical" -value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd" +value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd" ) (vvPair variable "package_name" @@ -306,7 +306,7 @@ value "struct" ) (vvPair variable "time" -value "15:06:49" +value "14:16:25" ) (vvPair variable "unit" @@ -314,7 +314,7 @@ value "ahbGpio_tb" ) (vvPair variable "user" -value "axel.amand" +value "remi.heredero" ) (vvPair variable "version" @@ -326,11 +326,11 @@ value "struct" ) (vvPair variable "year" -value "2023" +value "2024" ) (vvPair variable "yy" -value "23" +value "24" ) ] ) @@ -668,8 +668,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hReset_n : std_uLogic -" +st "SIGNAL hReset_n : std_uLogic" ) ) *13 (Net @@ -687,8 +686,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hClk : std_uLogic -" +st "SIGNAL hClk : std_uLogic" ) ) *14 (Net @@ -706,8 +704,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hResp : std_uLogic -" +st "SIGNAL hResp : std_uLogic" ) ) *15 (Net @@ -725,8 +722,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hReady : std_uLogic -" +st "SIGNAL hReady : std_uLogic" ) ) *16 (Net @@ -745,8 +741,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,32000,1200" -st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0) -" +st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" ) ) *17 (Net @@ -764,8 +759,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hSel : std_uLogic -" +st "SIGNAL hSel : std_uLogic" ) ) *18 (Net @@ -783,8 +777,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,15500,1200" -st "SIGNAL hWrite : std_uLogic -" +st "SIGNAL hWrite : std_uLogic" ) ) *19 (Net @@ -803,8 +796,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,32500,1200" -st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0) -" +st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)" ) ) *20 (Net @@ -823,8 +815,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,32000,1200" -st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0) -" +st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" ) ) *21 (Net @@ -843,8 +834,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,30000,1200" -st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 ) -" +st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )" ) ) *22 (Blk @@ -1616,8 +1606,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,28000,1200" -st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0) -" +st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)" ) ) *48 (Net @@ -1636,8 +1625,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,28000,1200" -st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0) -" +st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)" ) ) *49 (Net @@ -1656,8 +1644,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,28000,1200" -st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0) -" +st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)" ) ) *50 (Net @@ -1676,8 +1663,7 @@ isHidden 1 font "Courier New,9,0" ) xt "0,0,27500,1200" -st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0) -" +st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)" ) ) *51 (Wire @@ -2351,8 +2337,8 @@ tm "BdCompilerDirectivesTextMgr" ] associable 1 ) -windowSize "-8,-8,1928,1048" -viewArea "27426,17402,170102,94921" +windowSize "164,195,1039,926" +viewArea "49240,25632,103588,71748" cachedDiagramExtent "0,0,138000,93000" pageSetupInfo (PageSetupInfo ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool," @@ -2376,7 +2362,7 @@ boundaryWidth 0 ) hasePageBreakOrigin 1 pageBreakOrigin "29000,19000" -lastUid 13522,0 +lastUid 13575,0 defaultCommentText (CommentText shape (Rectangle layer 0 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd.bak b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd.bak new file mode 100644 index 0000000..018b5fa --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd.bak @@ -0,0 +1,4005 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "AhbLiteComponents_test" +duName "ahbGpio_tester" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 12657,0 +) +(Instance +name "I_DUT" +duLibraryName "AhbLiteComponents" +duName "ahbGpio" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +] +mwi 0 +uid 13194,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbGpio_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:06:49" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLiteComponents_test" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/AhbLiteComponents_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "ahbGpio_tb" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:06:49" +) +(vvPair +variable "unit" +value "ahbGpio_tb" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 198,0 +optionalChildren [ +*1 (Grouping +uid 1487,0 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"EdgeToEdgeStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "-8600,550,-8600,550" +) +header "" +) +elements [ +] +) +entityPath "" +) +defaultHdlText (HdlText +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,8000,10000" +) +ttg (MlTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*90 (Text +va (VaSet +font "Verdana,8,1" +) +xt "2950,3400,5250,4400" +st "eb1" +blo "2950,4200" +tm "HdlTextNameMgr" +) +*91 (Text +va (VaSet +font "Verdana,8,1" +) +xt "2950,4400,4150,5400" +st "1" +blo "2950,5200" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "250,8250,1750,9750" +iconName "UnknownFile.png" +iconMaskName "UnknownFile.msk" +) +viewiconposition 0 +) +defaultEmbeddedText (EmbeddedText +commentText (CommentText +ps "CenterOffsetStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg 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"3000,500,3000,500" +blo "3000,500" +tm "WireNameMgr" +) +) +) +defaultPortIoBuffer (PortIoBuffer +shape (CompositeShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +) +optionalChildren [ +(Hexagon +sl 0 +xt "500,-375,2000,375" +) +(Line +sl 0 +xt "0,0,500,0" +pts [ +"0,0" +"500,0" +] +) +] +) +stc 0 +sf 1 +tg (WTG +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "3000,500,3000,500" +blo "3000,500" +tm "WireNameMgr" +) +) +) +defaultSignal (Wire +shape (OrthoPolyLine +va (VaSet +vasetType 3 +) +pts [ +"0,0" +"0,0" +] +) +ss 0 +es 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,0,3400,1400" +st "sig0" +blo "0,1200" +tm "WireNameMgr" +) +) +) +defaultBus (Wire +shape (OrthoPolyLine +va (VaSet +vasetType 3 +lineWidth 2 +) +pts [ +"0,0" +"0,0" +] +) +ss 0 +es 0 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,0,4700,1400" +st "dbus0" +blo "0,1200" +tm "WireNameMgr" +) +) +) +defaultBundle (Bundle +shape (OrthoPolyLine +va (VaSet +vasetType 3 +lineColor "32768,0,0" +lineWidth 2 +) +pts [ +"0,0" +"0,0" +] +) +ss 0 +es 0 +sat 32 +eat 32 +textGroup (BiTextGroup +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "0,400,3700,1400" +st "bundle0" +blo "0,1200" +tm "BundleNameMgr" +) +second (MLText +va (VaSet +) +xt "0,1400,1500,2600" +st "()" +tm "BundleContentsMgr" +) +) +bundleNet &0 +) +defaultPortMapFrame (PortMapFrame +ps "PortMapFrameStrategy" +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,10000,12000" +) +portMapText (BiTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +first (MLText +va (VaSet +) +xt "0,0,5000,1200" +st "Auto list" +) +second (MLText +va (VaSet +) +xt "0,1200,9600,2400" +st "User defined list" +tm "PortMapTextMgr" +) +) +) +defaultGenFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 2 +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "0,-1400,18500,-200" +st "g0: FOR i IN 0 TO n GENERATE" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1050,1750" +) +num (Text +va (VaSet +) +xt "150,400,950,1400" +st "1" +blo "150,1200" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*92 (Text +va (VaSet +font "Verdana,8,1" +) +xt "11800,20000,21800,21000" +st "Frame Declarations" +blo "11800,20800" +) +*93 (MLText +va (VaSet +) +xt "11800,21000,11800,21000" +tm "BdFrameDeclTextMgr" +) +] +) +) +defaultBlockFrame (Frame +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 1 +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (MLText +va (VaSet +) +xt "0,-1400,11000,-200" +st "b0: BLOCK (guard)" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +ps "TopLeftStrategy" +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "50,50,1050,1750" +) +num (Text +va (VaSet +) +xt "150,400,950,1400" +st "1" +blo "150,1200" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*94 (Text +va (VaSet +font "Verdana,8,1" +) +xt "11800,20000,21800,21000" +st "Frame Declarations" +blo "11800,20800" +) +*95 (MLText +va (VaSet +) +xt "11800,21000,11800,21000" +tm "BdFrameDeclTextMgr" +) +] +) +style 3 +) +defaultSaCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1950" +st "Port" +blo "0,1750" +) +) +thePort (LogicalPort +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultSaCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1950" +st "Port" +blo "0,1750" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Port" +t "" +o 0 +) +) +) +defaultDeclText (MLText +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +) +archDeclarativeBlock (BdArchDeclBlock +uid 1,0 +stg "BdArchDeclBlockLS" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "29000,26800,36000,27800" +st "Declarations" +blo "29000,27600" +) +portLabel (Text +uid 3,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "29000,28000,32400,29000" +st "Ports:" +blo "29000,28800" +) +preUserLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "29000,27800,33800,28800" +st "Pre User:" +blo "29000,28600" +) +preUserText (MLText +uid 5,0 +va (VaSet +font "Courier New,10,0" +) +xt "31000,28800,59200,33600" +st "constant ioNb: positive := 8; + +constant clockFrequency : real := 60.0E6; +--constant clockFrequency : real := 66.0E6;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "29000,28000,38000,29000" +st "Diagram Signals:" +blo "29000,28800" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "29000,28000,35000,29000" +st "Post User:" +blo "29000,28800" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Courier New,10,0" +) +xt "31000,42400,31000,42400" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 122,0 +usingSuid 1 +emptyRow *96 (LEmptyRow +) +uid 3310,0 +optionalChildren [ +*97 (RefLabelRowHdr +) +*98 (TitleRowHdr +) +*99 (FilterRowHdr +) +*100 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*101 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*102 (GroupColHdr +tm "GroupColHdrMgr" +) +*103 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*104 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*105 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*106 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*107 (InitColHdr +tm "BlockDiagramInitColHdrMgr" +) +*108 (EolColHdr +tm "BlockDiagramEolColHdrMgr" +) +*109 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hReset_n" +t "std_uLogic" +o 5 +suid 108,0 +) +) +uid 12637,0 +) +*110 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hClk" +t "std_uLogic" +o 2 +suid 109,0 +) +) +uid 12639,0 +) +*111 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hResp" +t "std_uLogic" +o 6 +suid 110,0 +) +) +uid 12641,0 +) +*112 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hReady" +t "std_uLogic" +o 4 +suid 111,0 +) +) +uid 12643,0 +) +*113 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 3 +suid 112,0 +) +) +uid 12645,0 +) +*114 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hSel" +t "std_uLogic" +o 7 +suid 113,0 +) +) +uid 12647,0 +) +*115 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hWrite" +t "std_uLogic" +o 10 +suid 114,0 +) +) +uid 12649,0 +) +*116 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 8 +suid 115,0 +) +) +uid 12651,0 +) +*117 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 9 +suid 116,0 +) +) +uid 12653,0 +) +*118 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 117,0 +) +) +uid 12655,0 +) +*119 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "ioEn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 12 +suid 118,0 +) +) +uid 13250,0 +) +*120 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "ioOut" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 14 +suid 119,0 +) +) +uid 13252,0 +) +*121 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "ioIn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 13 +suid 120,0 +) +) +uid 13254,0 +) +*122 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "io" +t "std_logic_vector" +b "(ioNb-1 DOWNTO 0)" +o 11 +suid 122,0 +) +) +uid 13256,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 3323,0 +optionalChildren [ +*123 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *124 (MRCItem +litem &96 +pos 14 +dimension 20 +) +uid 3325,0 +optionalChildren [ +*125 (MRCItem +litem &97 +pos 0 +dimension 20 +uid 3326,0 +) +*126 (MRCItem +litem &98 +pos 1 +dimension 23 +uid 3327,0 +) +*127 (MRCItem +litem &99 +pos 2 +hidden 1 +dimension 20 +uid 3328,0 +) +*128 (MRCItem +litem &109 +pos 0 +dimension 20 +uid 12638,0 +) +*129 (MRCItem +litem &110 +pos 1 +dimension 20 +uid 12640,0 +) +*130 (MRCItem +litem &111 +pos 2 +dimension 20 +uid 12642,0 +) +*131 (MRCItem +litem &112 +pos 3 +dimension 20 +uid 12644,0 +) +*132 (MRCItem +litem &113 +pos 4 +dimension 20 +uid 12646,0 +) +*133 (MRCItem +litem &114 +pos 5 +dimension 20 +uid 12648,0 +) +*134 (MRCItem +litem &115 +pos 6 +dimension 20 +uid 12650,0 +) +*135 (MRCItem +litem &116 +pos 7 +dimension 20 +uid 12652,0 +) +*136 (MRCItem +litem &117 +pos 8 +dimension 20 +uid 12654,0 +) +*137 (MRCItem +litem &118 +pos 9 +dimension 20 +uid 12656,0 +) +*138 (MRCItem +litem &119 +pos 10 +dimension 20 +uid 13251,0 +) +*139 (MRCItem +litem &120 +pos 11 +dimension 20 +uid 13253,0 +) +*140 (MRCItem +litem &121 +pos 12 +dimension 20 +uid 13255,0 +) +*141 (MRCItem +litem &122 +pos 13 +dimension 20 +uid 13257,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 3329,0 +optionalChildren [ +*142 (MRCItem +litem &100 +pos 0 +dimension 20 +uid 3330,0 +) +*143 (MRCItem +litem &102 +pos 1 +dimension 50 +uid 3331,0 +) +*144 (MRCItem +litem &103 +pos 2 +dimension 100 +uid 3332,0 +) +*145 (MRCItem +litem &104 +pos 3 +dimension 50 +uid 3333,0 +) +*146 (MRCItem +litem &105 +pos 4 +dimension 100 +uid 3334,0 +) +*147 (MRCItem +litem &106 +pos 5 +dimension 100 +uid 3335,0 +) +*148 (MRCItem +litem &107 +pos 6 +dimension 50 +uid 3336,0 +) +*149 (MRCItem +litem &108 +pos 7 +dimension 80 +uid 3337,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 3324,0 +vaOverrides [ +] +) +] +) +uid 3309,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *150 (LEmptyRow +) +uid 3339,0 +optionalChildren [ +*151 (RefLabelRowHdr +) +*152 (TitleRowHdr +) +*153 (FilterRowHdr +) +*154 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*155 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*156 (GroupColHdr +tm "GroupColHdrMgr" +) +*157 (NameColHdr +tm "GenericNameColHdrMgr" +) +*158 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*159 (InitColHdr +tm "GenericValueColHdrMgr" +) +*160 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*161 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 3351,0 +optionalChildren [ +*162 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *163 (MRCItem +litem &150 +pos 0 +dimension 20 +) +uid 3353,0 +optionalChildren [ +*164 (MRCItem +litem &151 +pos 0 +dimension 20 +uid 3354,0 +) +*165 (MRCItem +litem &152 +pos 1 +dimension 23 +uid 3355,0 +) +*166 (MRCItem +litem &153 +pos 2 +hidden 1 +dimension 20 +uid 3356,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 3357,0 +optionalChildren [ +*167 (MRCItem +litem &154 +pos 0 +dimension 20 +uid 3358,0 +) +*168 (MRCItem +litem &156 +pos 1 +dimension 50 +uid 3359,0 +) +*169 (MRCItem +litem &157 +pos 2 +dimension 100 +uid 3360,0 +) +*170 (MRCItem +litem &158 +pos 3 +dimension 100 +uid 3361,0 +) +*171 (MRCItem +litem &159 +pos 4 +dimension 50 +uid 3362,0 +) +*172 (MRCItem +litem &160 +pos 5 +dimension 50 +uid 3363,0 +) +*173 (MRCItem +litem &161 +pos 6 +dimension 80 +uid 3364,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 3352,0 +vaOverrides [ +] +) +] +) +uid 3338,0 +type 1 +) +activeModelName "BlockDiag" +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs index 44d6c07..0d98860 100644 --- a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs @@ -4149,7 +4149,7 @@ hdsWorkspaceLocation "" relativeLibraryRootDir "" vmLabelLatestDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0 -logWindowGeometry "636x406+308+98" +logWindowGeometry "636x514+308+98" diagramBrowserTabNo 0 showInsertPortHint 0 showContentFirstTime 0 @@ -6031,6 +6031,96 @@ disableFilters 1 ] layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" ) +(Viewpoint_v2 +name "Parse Errors Report" +TreeListVPDatas [ +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "File Name" +width 150 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 120 +alignment 0 +) +(SmartTableVPData_Column +name "Location" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Absolute Path" +width 14 +alignment 1 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Instances" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "1" +filterColumn "Parse Error" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(A(C(LogicalObjects)))" +) ] WorkTabs [ (WorkTab @@ -6226,6 +6316,7 @@ activeViewpointIdx 0 ) ] ViewpointsOnOutlookBar [ +"Parse Errors Report" ] lastActiveViewpoint "Default Viewpoint" expandedTemplateNodes [ diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak index 28c9b8f..29b7fee 100644 --- a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak @@ -1280,6 +1280,7 @@ projectPaths [ "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" +"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" ] libMappingsRootDir "" teamLibMappingsRootDir "" @@ -1300,288 +1301,144 @@ exportedDirectories [ exportStdIncludeRefs 1 exportStdPackageRefs 1 ) -printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN" +printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN" pageSizes [ (PageSizeInfo -name "12\" x 18\"" -type 512 -width 1106 -height 1658 +name "Letter" +width 783 +height 1013 ) (PageSizeInfo -name "11\" x 17\"" -type 17 -width 1013 -height 1566 -) -(PageSizeInfo -name "Legal (8,5\" x 14\")" +name "Legal" type 5 width 783 height 1290 ) (PageSizeInfo -name "Letter (8,5\" x 11\")" -width 783 -height 1013 -) -(PageSizeInfo -name "Executive (7,25\"x10,5\")" -type 7 -width 667 -height 967 -) -(PageSizeInfo -name "5,5\" x 8,5\"" +name "Statement" type 6 width 506 height 783 ) (PageSizeInfo -name "A3 (297 x 420 mm)" +name "Executive" +type 7 +width 667 +height 967 +) +(PageSizeInfo +name "A3" type 8 width 1077 height 1523 ) (PageSizeInfo -name "A4 (210 x 297 mm)" +name "A4" type 9 width 761 height 1077 ) (PageSizeInfo -name "A5 (148 x 210 mm)" +name "A5" type 11 -width 538 +width 536 height 761 ) (PageSizeInfo -name "A6 (105 x 148 mm)" -type 70 -width 380 -height 538 -) -(PageSizeInfo -name "B4 JIS (257 x 364 mm)" +name "B4 (JIS)" type 12 width 932 height 1320 ) (PageSizeInfo -name "B5 JIS (182 x 257 mm)" +name "B5 (JIS)" type 13 width 660 height 932 ) (PageSizeInfo -name "B6 JIS (128 x 182 mm)" -type 88 -width 464 -height 660 +name "11×17" +type 17 +width 1013 +height 1566 ) (PageSizeInfo -name "8\" x 13\"" -type 518 -width 737 -height 1198 -) -(PageSizeInfo -name "8,25\" x 13\"" -type 519 -width 760 -height 1198 -) -(PageSizeInfo -name "8,5\" x 13\"" -type 14 -width 783 -height 1198 -) -(PageSizeInfo -name "8.5\" x 13.4\"" -type 551 -width 783 -height 1235 -) -(PageSizeInfo -name "Com10 Env.(4,125\"x9,5\")" +name "Envelope #10" type 20 -width 380 +width 379 height 875 ) (PageSizeInfo -name "Env.Monar.(3,875\"x7,5\")" -type 37 -width 357 -height 691 -) -(PageSizeInfo -name "Env. DL (110 x 220 mm)" +name "Envelope DL" type 27 width 399 height 798 ) (PageSizeInfo -name "Env. C6 (114 x 162 mm)" -type 31 -width 413 -height 587 -) -(PageSizeInfo -name "Env. C5 (162 x 229 mm)" +name "Envelope C5" type 28 width 587 height 830 ) (PageSizeInfo -name "8K (267 x 390 mm)" -type 520 -width 968 -height 1415 +name "Envelope B5" +type 34 +width 638 +height 907 ) (PageSizeInfo -name "16K (195 x 267 mm)" -type 521 -width 707 -height 968 +name "Envelope Monarch" +type 37 +width 357 +height 691 ) (PageSizeInfo -name "8,25\" x 14\"" -type 522 -width 760 -height 1290 +name "Japanese Postcard" +type 43 +width 362 +height 536 ) (PageSizeInfo -name "11\" x 14\"" -type 524 -width 1013 -height 1290 +name "A6" +type 70 +width 380 +height 536 ) (PageSizeInfo -name "13\" x 19,2\"" -type 525 -width 1198 -height 1769 +name "Double Japan Postcard Rotated" +type 82 +width 536 +height 725 ) (PageSizeInfo -name "13\" x 19\"" -type 526 -width 1198 -height 1751 +name "Executive (JIS)" +type 119 +width 783 +height 1196 ) (PageSizeInfo -name "12,6\" x 19,2\"" -type 527 -width 1161 -height 1769 +name "Oficio 8.5x13" +type 120 +width 783 +height 1198 ) (PageSizeInfo -name "12,6\" x 18,5\"" -type 528 -width 1161 -height 1704 -) -(PageSizeInfo -name "13\" x 18\"" -type 529 -width 1198 +name "12x18" +type 121 +width 1105 height 1658 ) (PageSizeInfo -name "10\" x 14\"" -type 16 -width 921 -height 1290 +name "8K 273x394 mm" +type 139 +width 990 +height 1428 ) (PageSizeInfo -name "10\" x 15\"" -type 546 -width 921 -height 1382 -) -(PageSizeInfo -name "11\" x 15\"" -type 539 -width 1013 -height 1382 -) -(PageSizeInfo -name "SRA3 (320 x 450 mm)" -type 530 -width 1161 -height 1632 -) -(PageSizeInfo -name "SRA4 (225 x 320 mm)" -type 531 -width 816 -height 1161 -) -(PageSizeInfo -name "Format papier personnalisé" -type 256 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size1(215,9 x 279,4 mm)" -type 257 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size2(215,9 x 279,4 mm)" -type 258 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size3(215,9 x 279,4 mm)" -type 259 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size4(215,9 x 279,4 mm)" -type 260 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size5(215,9 x 279,4 mm)" -type 261 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size6(215,9 x 279,4 mm)" -type 262 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size7(215,9 x 279,4 mm)" -type 263 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size8(215,9 x 279,4 mm)" -type 264 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size9(215,9 x 279,4 mm)" -type 265 -width 783 -height 1013 -) -(PageSizeInfo -name "Custom Paper Size10(215,9 x 279,4 mm)" -type 266 -width 783 -height 1013 +name "16K 197x273 mm" +type 140 +width 714 +height 990 ) ] exportPageSetupInfo (PageSetupInfo @@ -4292,7 +4149,7 @@ hdsWorkspaceLocation "" relativeLibraryRootDir "" vmLabelLatestDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0 -logWindowGeometry "636x406+-823+276" +logWindowGeometry "636x406+308+98" diagramBrowserTabNo 0 showInsertPortHint 0 showContentFirstTime 0 @@ -6174,6 +6031,96 @@ disableFilters 1 ] layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" ) +(Viewpoint_v2 +name "Parse Errors Report" +TreeListVPDatas [ +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "File Name" +width 150 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 120 +alignment 0 +) +(SmartTableVPData_Column +name "Location" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Absolute Path" +width 14 +alignment 1 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Instances" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "1" +filterColumn "Parse Error" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(A(C(LogicalObjects)))" +) ] WorkTabs [ (WorkTab @@ -6369,6 +6316,7 @@ activeViewpointIdx 0 ) ] ViewpointsOnOutlookBar [ +"Parse Errors Report" ] lastActiveViewpoint "Default Viewpoint" expandedTemplateNodes [ @@ -6384,11 +6332,10 @@ size 180 ] displayHierarchy 0 xPos 0 -yPos 0 -width 1936 -height 1056 +yPos 9 +width 974 +height 1047 activeSidePanelTab 2 -activeLibraryTab 1 sidePanelSize 278 showUnixHiddenFiles 0 componentBrowserXpos 569