From 9ceb15c0ff4be504ee75c0194ce2237df2c37224 Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 15 Mar 2024 15:03:34 +0100 Subject: [PATCH] add solutions --- .../Prefs/dp_user/v2_72/dp_user_prefs | 64 + .../01-WaveformGenerator/Prefs/hds.hdp | 19 + .../Prefs/hds_team/shared.hdp | 23 + .../Prefs/hds_team/v2018.1/hds_team_prefs | 55 + .../Prefs/hds_team/v2018.1/title_block.tmpl | 273 + .../Prefs/hds_team/v2019.2/hds_team_prefs | 55 + .../Prefs/hds_team/v2019.2/hds_team_prefs.bak | 55 + .../Prefs/hds_team/v2019.2/title_block.tmpl | 273 + .../Prefs/hds_team/v2019.3/hds_team_prefs | 55 + .../Prefs/hds_team/v2019.3/title_block.tmpl | 273 + .../hds_user-linux/v2019.3/hds_user_prefs | 6097 ++++ .../hds_user-linux/v2019.3/tasks/generate.tsk | 41 + .../v2019.3/tasks/modelsim_compile.tsk | 98 + .../v2019.3/tasks/modelsim_flow.tsk | 83 + .../v2019.3/tasks/modelsim_simulate.tsk | 98 + .../v2019.3/tasks/prepare_for_synthesis.tsk | 162 + .../tasks/xilinx_project_navigator.tsk | 114 + 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+[LexParser] +[Editor] +recentFile0=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl +lastFilter=.vhdl +mark.lineImage=blueball +[Printer] +ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript +[ToolbarFrames] +geom0Group1=top H +geom0Group2=top H +geom0Group3=top H +state0Search=1 +Num=0 +state0VersionManagement=1 +state0Tasks=1 +state0View=1 +state0Standard=1 +state0Edit=1 +Group1=Standard Search +Group2=Edit Bookmarks View Macros DocumentTools Windows +Group3=VersionManagement Tasks +state0Macros=1 +state0Bookmarks=1 +state0Windows=1 +state0DocumentTools=1 +[LexParser.LexPSL] +[DND] +TrackerBg=#c3c3c3 +signalAcceptDropBg=white +signalRefuseDropBg=red +[General] +[Browser] +normalTextBg=white +normalTextFg=black +[Replace] +historyMax=4 +atomicReplaceAll=No +[Console] +[Templates] +Visibility=No +[SearchInFiles] +SearchAsRegExp=0 +MatchCase=0 +LookInSubfolders=0 +historyMax=4 +[VDiff] +[R72] +indentType=spaces +indentString=\#\#\# +[TCOM] +logTCOMActivity=No +afterIdleHandlerTimeSlice=300 +[Menus] +DocAndVis= +[Help] +default=te_guide +[Plugins] +userLanguages= +[Search] +historyMax=4 +[Geometry] +TopWindow0=1286x981+317+1103 +FrameSupp0,0=165 diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds.hdp b/zz-solutions/01-WaveformGenerator/Prefs/hds.hdp new file mode 100644 index 0000000..b986ef0 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds.hdp @@ -0,0 +1,19 @@ +[Concat] +[ModelSim] +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hdl +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/shared.hdp b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs.bak @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..87d40fc --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6097 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first 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+"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/01-WaveformGenerator/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_labs/01-WaveformGenerator/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "task_DesignCompilerPath" +second "" +) +(pair +first "task_LeonardoPath" +second "" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +(pair +first "task_NC-SimPath" +second "" +) +(pair +first "task_PrecisionRTLPath" +second "" +) +(pair +first "task_QuestaSimPath" +second "" +) +(pair +first "task_VCSPath" +second "" +) +] +defaultCategoryTemplates [ +1 +"architecture.vhd" +] +defaultCategoryTemplatesPrefs [ +1 +0 +] +tasksOrder [ +"USER:Generate" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:ModelSim Flow" +"USER:Xilinx Project Navigator" +"USER:Prepare for Synthesis" +] +tasksToolbarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" 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b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7348b0e --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/waveformGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description 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+interruptPointShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +linkShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +linkNameVaSet (VaSet +font "Verdana,9,1" +) +exitPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) +wStateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "26368,26368,26368" +lineWidth 2 +) +wStateTextVaSet (VaSet +fg "0,0,32768" +font "Verdana,12,1" +) +tBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +) +tBlockActionsVaSet (VaSet +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +localDeclValueVaSet (VaSet +font "Courier New,8,0" +) +processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/generate.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..91575dd --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6800 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction 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+processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7348b0e --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/waveformGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/01-WaveformGenerator/Scripts/.gitlab-ci.yml b/zz-solutions/01-WaveformGenerator/Scripts/.gitlab-ci.yml new file mode 100644 index 0000000..9d1d7af --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/.gitlab-ci.yml @@ -0,0 +1,53 @@ +stages: + - deploy + +image: alpine:latest + +scripts: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployScriptsAll.bash + - deployScripts.bash + - /*.{pl} + - when: manual + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Bash" + - apk add bash + - echo "Install Core Utils" + - apk add coreutils + - echo "Install Git" + - apk add git + - echo "Set Git credentials" + - git config --global user.email "silvan.zahno@hevs.ch" + - git config --global user.name "Silvan Zahno" + - echo "Setting up deploy-eda_scripts environment" + + script: + - bash ./deployScriptsAll.bash + +libs_trigger: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployLibsAll.bash + - deployLibs.bash + - when: manual + variables: + GIT_CHECKOUT: "false" + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Curl" + - apk add curl + + script: + - 'curl -X POST --fail -F token=glptt-0235c37f03e3060733df7d1151555fd0c63d0adb -F ref=master "https://gitlab.hevs.ch/api/v4/projects/762/trigger/pipeline"' diff --git a/zz-solutions/01-WaveformGenerator/Scripts/LICENSE b/zz-solutions/01-WaveformGenerator/Scripts/LICENSE new file mode 100644 index 0000000..fdf8bfa --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/LICENSE @@ -0,0 +1,11 @@ +All Rights Reserved + +Copyright (c) 2019 - HES-SO Valais Wallis + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/README.md b/zz-solutions/01-WaveformGenerator/Scripts/README.md new file mode 100644 index 0000000..618a38f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/README.md @@ -0,0 +1,238 @@ +

+
+ EDA scripts Logo +
+ Hevs EDA Scripts +
+

+ +

Common Files and Scripts for ELN Laboratories practical sessions.

+ +[![pipeline status](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/pipeline.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) +[![coverage report](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/coverage.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) + +# Table of contents +

+ Description • + How To Use • + Download • + Credits • + License + Find us on +

+ +## Description +[(Back to top)](#table-of-contents) + +These scripts can be used as for: +**Git Repos** +* [EDA_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +* [ELN_labs](https://gitlab.hevs.ch/course/ElN/eln_labs.git) +* [SEm_exams](https://gitlab.hevs.ch/course/SEm/exams.git) +* [ELN_chrono](https://gitlab.hevs.ch/course/ElN/eln_chrono.git) +* [ELN_cursor](https://gitlab.hevs.ch/course/ElN/eln_cursor.git) +* [ELN_kart](https://gitlab.hevs.ch/course/ElN/eln_kart.git) +* [ELN_inverter](https://gitlab.hevs.ch/course/ElN/eln_inverter.git) +* [ELN_synchro](https://gitlab.hevs.ch/course/ElN/eln_synchro.git) +* [SEm_labs](https://gitlab.hevs.ch/course/SEm/sem_labs.git) +* [ELN-kart](https://gitlab.hevs.ch/course/ElN/eln_kart_sodimm200.git) +* [ELN-display](https://gitlab.hevs.ch/course/ElN/eln_display.git) + +**SVN Repos** +* [CanSat](https://repos.hevs.ch/svn/eda/VHDL/labs/CanSat) (TODO) :rotating_light: +* [ELN_support](https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_support) (TODO) :rotating_light: +* [EPTM_AudioAmp](https://repos.hevs.ch/svn/eda/VHDL/labs/AudioAmp) (TODO) :rotating_light: +* [EPTM_Radio](https://repos.hevs.ch/svn/eda/VHDL/labs/EPTM_radio) (TODO) :rotating_light: +* ... + +### Files +**Linux** +* ``changeDefaultViews.bash`` - Changes RTL <=> studentVersion + * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` + * Usage master => student: ``changeDefaultViews.bash -v -a master@version -n student@version`` + * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` + * Usage student => master: ``changeDefaultViews.bash -v -a student@version -n master@version`` + * Note: use the ``-r`` otion to also delete the specified actual_view +* ``cleanGenerated.bash`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bash`` +* ``hdlDesigner.bash`` - Main script for starting HDL-Designer +* ``deployLibs.bash`` - Execution from eln_libs repo, copy required libraries to student repo and commit/push it. + * Usage: ``./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployLibsAll.bash`` - Execution from eln_libs repo, copy required libraries to all student repo's and commit/push it. + * Usage: ``./Scripts/deployLibsAll.bash`` +* ``deployLab.bash`` - Execution from Laborepo, copy required laboratory files to student repo and commits/push it. + * Usage: ``./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScripts.bash`` - Copy required scripts to student repo and commits/push it. + * Usage: ``./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScriptsAll.bash`` - Execution from eln_scripts repo, copy required scripts to all student repo's and commit/push it. + * Usage: ``./deployScriptsAll.bash`` + +**Windows** +* ``cleanGenerated.bat`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bat`` +* ``cleanScratch.bat`` - Delete scratch directory + * Usage: +``` bash +set SCRATCH_DIR=C:\temp\eda\%username% +./cleanScratch.bat +``` + +* ``hdlDesigner.bat`` - Main script for starting HDL-Designer +* ``searchPaths.bat`` - Search for required Libraries and tools + * Usage: +``` bash +:: Define required Tools to be present +set REQUIRE_LIBS=1 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=1 +set REQUIRE_LIBERO=0 +set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries +set HDS_HOME=C:\eda\MentorGraphics\HDS +set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +set ISE_VERSION=14.7 +set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +set LIBERO_HOME=C:\eda\Microsemi\Libero +set design_name=eln_labs +./searchPaths.bat +``` + +**Perl Scripts** +Perl scripts are used to launch different tasks from HDL-Designer +* ``trimLibs.pl`` - Comment regular libraries in an concatenated file + * Parameter : ``trimlibs.pl `` +* ``update_ise.pl`` - + * Parameter : ``update_ise.pl `` +* ``update_libero.pl`` - + * Parameter : ``update_libero.pl `` +* ``start_libero.pl`` - + * Parameter : ``start_libero.pl `` + +## How To Use +[(Back to top)](#table-of-contents) + +To clone and run this application, you'll need [Git](https://git-scm.com) installed on your computer. +This repo is normally used as submodule to the laboratories and projects. + +To deploy the studentVersion to github cd to root of Labor master repo: +```bash +cd eln_labs +./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLab.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLab.bash -v -p isc-eln-labs -r https://github.com/hei-isc-eln/eln-labs.git + +cd sem_labs +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 01-WaveformGenerator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 02-SplineInterpolator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 03-DigitalToAnalogConverter +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 04-Lissajous +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 05-Morse +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 06-07-08-09-SystemOnChip +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 10-PipelinedOperators + +cd eln_chrono +./Scripts/deployLab.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git + +cd eln_cursor +./Scripts/deployLab.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git + +cd eln-display +./Scripts/deployLab.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git + +cd eln-kart +./Scripts/deployLab.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +``` + +To deploy the Libraries to github cd to root of Libs master repo: +```bash +./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./Scripts/deployLibs.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./Scripts/deployLibs.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./Scripts/deployLibs.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./Scripts/deployLibs.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./Scripts/deployLibs.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./Scripts/deployLibs.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./Scripts/deployLibs.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +./Scripts/deployLibs.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./Scripts/deployLibsAll.bash +``` + +To deploy the Scripts to github cd root of Scripts master Repo +```bash +./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./deployScripts.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./deployScripts.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./deployScripts.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./deployScripts.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./deployScripts.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./deployScripts.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./deployScripts.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./deployScripts.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./deployScripts.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-display.git +./deployScripts.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./deployScriptsAll.bash +``` + +
+![eln labs deployment](img/eln_labs_deployment-staff.png) +
+ +### Download +```bash +# Clone repo including submodules +git clone --recursive +``` + +### Pull changes repo and submodules +```bash +# Pull all changes in the repo including changes in the submodules (of given commit) +git pull --recurse-submodules +``` + +#### Update to latest commit +Update submodule to latest commit and update parentrepo +```bash +# Update submodule to latest commit +git submodule update --remote --merge + +# Afterwared you need to commit in the parentrepo the new pointer to the new commit in the submodule +git commit -am "Update submodule to latest commit" +``` + +### Add submodule +If the folder ``Scripts`` already exists, delete it and commit these changes. +Add submodule and define the master branch as the one you want to track +```bash +git submodule add -b master +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_scripts.git Scripts +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_libs.git Libs + +git submodule init + +git submodule update +``` + +## Credits +[(Back to top)](#table-of-contents) +* COF +* PRC +* ZAS +* AMA + +## License +[(Back to top)](#table-of-contents) + +:copyright: [All rights reserved](LICENSE) + +--- + +## Find us on +> Website [hevs.ch](https://www.hevs.ch)  ·  +> LinkedIn [HES-SO Valais-Wallis](https://www.linkedin.com/groups/104343/)  ·  +> Youtube [HES-SO Valais-Wallis](https://www.youtube.com/user/HESSOVS) +> Twitter [@hessovalais](https://twitter.com/hessovalais)  ·  +> Facebook [@hessovalais](https://www.facebook.com/hessovalais)  ·  \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/changeDefaultViews.bash b/zz-solutions/01-WaveformGenerator/Scripts/changeDefaultViews.bash new file mode 100644 index 0000000..be6fa62 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/changeDefaultViews.bash @@ -0,0 +1,94 @@ +#!/bin/bash + +#================================================================================ +# changeDefaultViews.bash - change HDL Project views +# * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` +# * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` +# * Usage: add ``-r`` for deleting the specified actual view **dangerous** +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +project_directory='' +actual_view='masterVersion' +new_view='studentVersion' + +usage='Usage: changeDefaultViews.bash [-p projectDir] [-r] [-v] [-h]' +while getopts 'p:a:n:rvh' options; do + case $options in + p ) project_directory=$OPTARG;; + a ) actual_view=$OPTARG;; + n ) new_view=$OPTARG;; + r ) delete_actual_view=1;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done +if [ -z "$project_directory" ]; then + project_directory="$base_directory" +else + project_directory="$base_directory/$project_directory" +fi + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Changing default views for HDL Designer" + echo "${INDENT}in $project_directory" + echo "${INDENT}from $actual_view to $new_view" + if [ -n "$delete_actual_view" ] ; then + echo "Delete all $actual_view in $project_directory" + fi +fi + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Change views in configuration files +# +find $project_directory -type f -name '*._epf' \ + | xargs sed -i "s/$actual_view/$new_view/g" + +#------------------------------------------------------------------------------- +# Remove all acutal views File +# +if [ -n "$delete_actual_view" ] ; then + project_directory=`realpath $project_directory` + echo $project_directory + echo "Delete $actual_view" + find $project_directory/ -type f -iname "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -iname "*$actual_view*" -exec rm {} \; + # For HDL Designer file naming convention + # making uppercase letters to @lowercase masterVersion = master@version + actual_view="$(sed -E s/\([A-Z]\)/@\\L\\1/g <<< $actual_view)" + find $project_directory/ -type f -name "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -name "*$actual_view*" -exec rm {} \; + +fi + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bash b/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bash new file mode 100644 index 0000000..ca088c6 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bat b/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/cleanScratch.bat b/zz-solutions/01-WaveformGenerator/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deployLab.bash b/zz-solutions/01-WaveformGenerator/Scripts/deployLab.bash new file mode 100644 index 0000000..10652b0 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deployLab.bash @@ -0,0 +1,559 @@ +#!/bin/bash + +#================================================================================ +# deployLab.bash - updates github repos for individual labos +# Example usage 01: ./Scripts/deployLab.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 02: ./Scripts/deployLab.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 03: ./Scripts/deployLab.bash -v -p isc-did-labs -r https://github.com/hei-isc-eln/did-labs.git +# Example usage 04: ./Scripts/deployLab.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 05: ./Scripts/deployLab.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 06: ./Scripts/deployLab.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 07: ./Scripts/deployLab.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 08: ./Scripts/deployLab.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 09: ./Scripts/deployLab.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git + +# Example usage 10: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 11: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 12: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +# Example usage 13: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +# Example usage 14: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +# Example usage 15: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +# Example usage 16: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +# Example usage 17: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +# Example usage 18: ./Scripts/deployLab.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -s 1 +# Example usage 19: ./Scripts/deployLab.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='synd-did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +dir='01-StepperMotor' +sourceDirUp=0 + +usage='Usage: deployLab.bash [-p projectName] [-r repourl] [-d directory] [-s sourceDirUp] [-v] [-h]' +while getopts 'p:r:d:s:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) dir=$OPTARG;; + s ) sourceDirUp=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Laboratory for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "${INDENT}in $dir" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +repo_dest=`realpath "./"` +repo_source="./" +# If Scripts folder is at root of project, needs to get up 3 times (scripts, project name, tmp) +# If more is needed (i.e. see car-labs structure), can be added with -s switch +for ((i=0;i<$sourceDirUp+3;i++)); do + repo_source="$repo_source/.." +done +repo_source=`realpath "$repo_source"` + +echo "Update files in student repo $project" +# Copy needed files per project +if [ "$project" == "synd-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "ete-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "isc-did-labs" ]; then + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "car-labs" ]; then + # bem + echo "copy $repo_source/bem" + cp -ar "$repo_source/bem" ./ + # isa + echo "copy $repo_source/isa" + cp -ar "$repo_source/isa" ./ + # heirv32_sc + mkdir -p heirv32_sc + # copy root files except some specific ones + find $repo_source/hdl -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest/heirv32_sc \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source/hdl -maxdepth 1 -type d ) + do + if [[ "$repo_source/hdl" != "$folder" && "$repo_source/hdl/.git" != "$folder" && "$repo_source/hdl/Libs" != "$folder" && "$repo_source/hdl/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder heirv32_sc/ + else + echo "skip $folder" + fi + done + + rm -v -f heirv32_sc/Board/concat/concatenated.vhd + rm -v -f heirv32_sc/Board/concat/car-labs.vhd + + rm -v -f heirv32_sc/HEIRV32/hdl/ALU_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/extend_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/hds/alu@decoder + rm -v -f heirv32_sc/HEIRV32/hds/_aludecoder._epf + + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/SingleCycle/hds/main@decoder + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hds/_maindecoder._epf + + rm -v -f heirv32_sc/Simulation/empty_ram.txt + +elif [ "$project" == "car-heirv" ]; then + # heirv32_mc + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source/" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + + rm -v -f ./Board/concat/concatenated.vhd + rm -v -f ./Board/concat/car-labs.vhd + + rm -v -f ./HEIRV32/hdl/ALU_rtl.vhd + rm -v -f ./HEIRV32/hdl/extend_rtl.vhd + rm -v -f ./HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f ./HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r ./HEIRV32/hds/alu@decoder + rm -v -f ./HEIRV32/hds/_aludecoder._epf + + rm -v -f ./HEIRV32/MultiCycle/hdl/instrdecoder_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_fsm.vhg + rm -v -f -r ./HEIRV32/MultiCycle/hds/instr@decoder + rm -v -f -r ./HEIRV32/MultiCycle/hds/main@f@s@m + rm -v -f ./HEIRV32/MultiCycle/hds/_instrdecoder._epf + rm -v -f ./HEIRV32/MultiCycle/hds/_mainfsm._epf + + rm -v -f ./HEIRV32_test/hdl/universalTester_test.vhd + rm -v -f -r ./HEIRV32_test/hds/universal@tester + rm -v -f ./HEIRV32_test/hds/_universaltester._epf + + rm -v -f ./Simulation/code_mc_disassembled.svg + rm -v -f ./Simulation/code_mc_disassembled_labels.svg + rm -v -f ./Simulation/code_mc_ghidra_labels.png + rm -v -f ./Simulation/empty_ram.txt + + #search='design_root = Board.ebs2_sc(struct)ebs2_sc/struct.bd' + #replace='design_root = Board.ebs2_mc(struct)ebs2_mc/struct.bd' + #sed -i "s/$search/$replace" Prefs/hds.hdp + +elif [ "$project" == "ele_labs" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "sem-labs" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/01-WaveformGenerator/Scripts" != "$folder" && "$repo_source/02-SplineInterpolator/Scripts" != "$folder" && "$repo_source/03-DigitalToAnalogConverter/Scripts" != "$folder" && "$repo_source/04-Lissajous/Scripts" != "$folder" && "$repo_source/05-Morse/Scripts" != "$folder" && "$repo_source/06-07-08-09-SystemOnChip/Scripts" != "$folder" && "$repo_source/10-PipelinedOperators/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for sem-labs $dir" + + if [ "$dir" == "01-WaveformGenerator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "02-SplineInterpolator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "03-DigitalToAnalogConverter" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "04-Lissajous" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "05-Morse" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "06-07-08-09-SystemOnChip" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "10-PipelinedOperators" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-cursor" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-cursor" + rm -v -f ./Cursor/hdl/amplitudeControl_RTL.vhd + rm -v -f ./Cursor/hdl/bridgeControl_RTL.vhd + rm -v -f ./Cursor/hdl/decelerationPositions_RTL.vhd + rm -v -f ./Cursor/hdl/divider_RTL.vhd + rm -v -f ./Cursor/hdl/findDistance_RTL1.vhd + rm -v -f ./Cursor/hdl/positionCounter_RTL.vhd + rm -v -f ./Cursor/hdl/pulseWidthModulator_RTL.vhd + rm -v -f ./Cursor/hds/_amplitudecontrol._epf + rm -v -f ./Cursor/hds/_bridgecontrol._epf + rm -v -f ./Cursor/hds/_control._epf + rm -v -f ./Cursor/hds/_decelerationpositions._epf + rm -v -f ./Cursor/hds/_divider._epf + rm -v -f ./Cursor/hds/_positioncounter._epf + rm -v -f ./Cursor/hds/_pulsewidthmodulator._epf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationpositions_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationPositions_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_findDistance_RTL1.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positioncounter_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positionCounter_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulsewidthmodulator_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulseWidthModulator_RTL.vhd._fpf + rm -v -f -r ./Cursor/hds/amplitude@control + rm -v -f -r ./Cursor/hds/bridge@control + rm -v -f -r ./Cursor/hds/control + rm -v -f -r ./Cursor/hds/deceleration@positions + rm -v -f -r ./Cursor/hds/divider + rm -v -f -r ./Cursor/hds/position@counter + rm -v -f -r ./Cursor/hds/pulse@width@modulator + rm -v -f -r ./Cursor/hds/rising@detector + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-cursor.vhd + +elif [ "$project" == "did-chrono" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-chrono" + rm -v -f ./Chronometer/hdl/coilControl_RTL.vhd + rm -v -f ./Chronometer/hdl/divider1Hz_RTL.vhd + rm -v -f ./Chronometer/hdl/tickLengthCounter_RTL.vhd + rm -v -f ./Chronometer/hdl/lcdDisplay_masterVersion.vhd + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_control._epf + rm -v -f ./Chronometer/hds/_divider1hz._epf + rm -v -f ./Chronometer/hds/_ticklengthcounter._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilcontrol_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilControl_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1hz_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1Hz_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_ticklengthcounter_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_tickLengthCounter_RTL.vhd._fpf + rm -v -f -r ./Chronometer/hds/coil@control/ + rm -v -f -r ./Chronometer/hds/control/ + rm -v -f -r ./Chronometer/hds/divider1@hz/ + rm -v -f -r ./Chronometer/hds/rising@detector/ + rm -v -f -r ./Chronometer/hds/tick@length@counter/ + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-chrono.vhd + +elif [ "$project" == "did-kart-ebs2" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs2 $dir" + + if [ "$dir" == "01-StepperMotor" ]; then + rm -v -f ./01-StepperMotor/StepperMotor/hdl/angleDifference_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/coilControl_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/stepperCounter_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hds/angle@control/master@version.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_shift@reg.bd + elif [ "$dir" == "02-DcMotor" ]; then + rm -v -f ./02-DcMotor/DcMotor/hdl/dcMotorPwm_RTL.vhd + elif [ "$dir" == "03-Sensors" ]; then + rm -v -f ./03-Sensors/Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./03-Sensors/Sensors/hdl/ultrasoundRanger_RTL.vhd + elif [ "$dir" == "04-Controller" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-kart-ebs3" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs3" + rm -v -f ./DcMotor/hdl/dcMotorPwm_RTL.vhd + rm -v -f ./Kart_test/hdl/txFIFO_tester_test.vhd + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tb/ + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tester/ + rm -v -f ./Kart_test/hds/_txfifo_tb._epf + rm -v -f ./Kart_test/hds/_txfifo_tester._epf + rm -v -f -r ./Kart_test/hds/kart@controller_full_tb/ + rm -v -f ./Kart_test/hds/_kartcontroller_full_tb._epf + rm -v -f ./Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./Sensors/hdl/ultrasoundRanger_RTL.vhd + rm -v -f ./Stepper/hdl/angleDifference_RTL.vhd + rm -v -f ./Stepper/hdl/coilControl_RTL.vhd + rm -v -f ./Stepper/hdl/stepperCounter_RTL.vhd + rm -v -f ./Stepper/hds/angle@control/master@version.bd + rm -v -f ./Stepper/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./Stepper/hds/coil@control/master@version_shift@reg.bd + rm -v -f ./Stepper_test/hdl/stepperMotorRegisters_tester_test.vhd + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tb/ + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tester/ + rm -v -f ./Stepper_test/hds/_steppermotorregisters_tb._epf + rm -v -f ./Simulation/Kart/UVM/uvmCommands.txt + rm -v -f ./Simulation/Kart/kartUVM.do + rm -v -f ./Simulation/Kart/txFIFO.do + rm -v -f ./Simulation/Stepper/stepperMotorRegisters.do + rm -v -f -r ./Simulation/UART/ + rm -v -f -r ./UART_test/ + + rm -v -f ./Board/concat/*.vhd + find ./Board/libero/designer/ ! \( -name "*.prjx" -o -name "*.adb" -o -name "*.ide_des" -o -name "*.pdb" -o -name "*_syn.prj" \) -type f -exec rm -v -f -r {} + + rm -v -f -r ./Documentation/ + rm -v -f -r ./CommandInterpreter/src/ + +elif [ "$project" == "did-synchro" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-synchro" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-synchro.vhd + +elif [ "$project" == "did-inverter" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-inverter" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-inverter.vhd + +elif [ "$project" == "did-display" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-display" + find ./Board/ise/ -name "*.mcs" -type f -exec rm -v -f {} + + rm -v -f -r ./Display/concat/ + find ./Display/hdl/ -name "*.vhg" -type f -exec rm -v -f {} + + rm -v -f ./Display/hdl/test_pattern_calculated_rtl.vhd + rm -v -f ./Display/hdl/vgaDataCreator_rgb.vhd + rm -v -f ./Display/hdl/vgaDataSelector_rtl.vhd + rm -v -f ./Display/hds/display@circuit/master@version.bd + rm -v -f -r ./Display/hds/vga@data@calculated/ + rm -v -f -r ./Display/hds/vga@data@selector/ + + rm -v -f -r ./Display_test/concat/ + + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-display.vhd + +elif [ "$project" == "eln_support" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_radio" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_audioamp" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "cansat" ]; then + echo "Error: Not implemented yet" +fi + +echo "Source taken from $repo_source to $repo_dest" + +#------------------------------------------------------------------------------- +# change from masterVersion to studentVersion and delete all masterVersion +# +if [ "$project" == "synd-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "ete-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "isc-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +else + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a master@version -n student@version -r +fi + +# add/commit/push changes to student repo +git add -A +git commit -a -m "$DATE: Automatic Laboratory Update with ``deployLab.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +echo "Delete tmp directory" +cd .. +pwd +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deployLibs.bash b/zz-solutions/01-WaveformGenerator/Scripts/deployLibs.bash new file mode 100644 index 0000000..3498c2b --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deployLibs.bash @@ -0,0 +1,320 @@ +#!/bin/bash + +#================================================================================ +# deployLibs.bash - updates github repos for individual labos +# indend to push libs from [DiD-libs](https://gitlab.hevs.ch/course/did/did-libs.git) +# Example usage 1: ./Scripts/deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +# Example usage 12: ./Scripts/deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' + +usage='Usage: deployLibs.bash [-p projectName] [-r repourl] [-v] [-h]' +while getopts 'p:r:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Libraries for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_dest=`realpath "./Libs"` +library_source=`realpath "./../../.."` +mkdir -p $library_dest + +# Copy needed libraries per project +echo "Update files in student repo $project" +if [ "$project" == "synd-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "ete-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "isc-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "car-labs" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + library_dest=`realpath "./heirv32_sc/Libs"` + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "car-heirv" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "ele_labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, Memory, Modulation, NanoBlaze" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/Modulation" "$library_dest/" + cp -ar "$library_source/Modulation_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "sem-labs" ]; then + echo " Copy libraries: Common, RS232, AhbLite, Memory, RiscV, NanoBlaze" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RiscV" "$library_dest/" + cp -ar "$library_source/RiscV_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "did-cursor" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "did-chrono" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + #cp -ar "$library_source/RS232" "$library_dest/" + #cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs2" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs3" ]; then + echo " Copy libraries: Common, Gates, I2C, Memory, RS232, IO, Sequential, UVM" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/UVM" "$library_dest/" + cp -ar "$library_source/UVM_test" "$library_dest/" +elif [ "$project" == "did-synchro" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-inverter" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Cordic" "$library_dest/" + cp -ar "$library_source/Cordic_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "eln_support" ]; then + echo "Nothing todo, no Libararies needed" +elif [ "$project" == "did-display" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "eptm_radio" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" +elif [ "$project" == "eptm_audioamp" ]; then + echo " Copy libraries: AD_DA, Common, Filter" + cp -ar "$library_source/AD_DA" "$library_dest/" + cp -ar "$library_source/AD_DA_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Filter" "$library_dest/" + cp -ar "$library_source/Filter_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "cansat" ]; then + echo " Copy libraries: AhbLite, AhbLiteComponents, Common, Commandline, Memory, NanoBlaze, RS232" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Commandline" "$library_dest/" + cp -ar "$library_source/Commandline_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Library Update with ``deployLibs.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deployLibsAll.bash b/zz-solutions/01-WaveformGenerator/Scripts/deployLibsAll.bash new file mode 100644 index 0000000..46c6c3c --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deployLibsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployLibsAll.bash - updates github repos for all labo's at once +# indend to push libs from [eda_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployLibs.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +./deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deploySEmLabs.bash b/zz-solutions/01-WaveformGenerator/Scripts/deploySEmLabs.bash new file mode 100644 index 0000000..b36ba70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deploySEmLabs.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#================================================================================ +# deployLabsAll.bash - updates github repos for all labo's at once +# indend to push labs from [sem-labs](https://gitlab.hevs.ch/course/SEm/hd-labs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + + +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deployScripts.bash b/zz-solutions/01-WaveformGenerator/Scripts/deployScripts.bash new file mode 100644 index 0000000..a91e55b --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deployScripts.bash @@ -0,0 +1,331 @@ +#!/bin/bash + +#================================================================================ +# deployScripts.bash - updates github repos for individual labos +# indend to push scripts from [DiD-scripts](https://gitlab.hevs.ch/course/did/did-scripts.git) +# Example usage 1: ./Scripts/deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +# Example usage 12: ./Scripts/deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory" + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +destdir='' + +usage='Usage: deployScripts.bash [-p projectName] [-r repourl] [-d destdir] [-v] [-h]' +while getopts 'p:r:d:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) destdir=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Scripts for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_source=`realpath "./../.."` + +# DiD Kart (EBS2 version) has a different project structure +if [ "$project" == "did-kart-ebs2" ]; then + # Copy needed libraries per project + mkdir -p "01-StepperMotor/Scripts" + library_dest=`realpath "./01-StepperMotor/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + + # Copy needed libraries per project + mkdir -p "02-DcMotor/Scripts" + library_dest=`realpath "./02-DcMotor/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "03-Sensors/Scripts" + library_dest=`realpath "./03-Sensors/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "04-Controller/Scripts" + library_dest=`realpath "./04-Controller/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + +# SEm Labs has also a different project structure +elif [ "$project" == "sem-labs" ]; then + # Copy needed libraries per project + mkdir -p "01-WaveformGenerator/Scripts" + library_dest=`realpath "./01-WaveformGenerator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "02-SplineInterpolator/Scripts" + library_dest=`realpath "./02-SplineInterpolator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "03-DigitalToAnalogConverter/Scripts" + library_dest=`realpath "./03-DigitalToAnalogConverter/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "04-Lissajous/Scripts" + library_dest=`realpath "./04-Lissajous/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "05-Morse/Scripts" + library_dest=`realpath "./05-Morse/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "06-07-08-09-SystemOnChip/Scripts" + library_dest=`realpath "./06-07-08-09-SystemOnChip/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "10-PipelinedOperators/Scripts" + library_dest=`realpath "./10-PipelinedOperators/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + +else + + if [ -n "$destdir" ]; then + mkdir -p "$destdir/Scripts" + library_dest=`realpath "$destdir/Scripts"` + else + mkdir -p "Scripts" + library_dest=`realpath "./Scripts"` + fi + + # Copy needed libraries per project + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/update_diamond.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + cp -arf "$library_source/start_diamond.pl" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Scripts Update with ``deployScripts.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +#s +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/deployScriptsAll.bash b/zz-solutions/01-WaveformGenerator/Scripts/deployScriptsAll.bash new file mode 100644 index 0000000..bb9e937 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/deployScriptsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployScriptsAll.bash - updates github Scripts folder for all labo's at once +# indend to push scripts from [eda_scripts](https://gitlab.hevs.ch/course/ElN/eda_scripts.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployScripts.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +./deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/generateSSHKey.bash b/zz-solutions/01-WaveformGenerator/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bash b/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bash new file mode 100644 index 0000000..4b54b46 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bat b/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..87ed140 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/hdlDesigner.bat @@ -0,0 +1,278 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... 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z5slpcST}!$8~P7WhC{jTkZBebrDfGX>qt%S4M-;Nv$%o<= zszHu|jpJD5?qJimvJMdQpFucx+aITouUdP_+smI6qL_!#ugDh zN}&D!wbIJZ=~NM2OaCmL(JE0eo`y7Ps(3hK2h=w5YoGVQc9Ny|U|vqAtCg!0C$0W9 z0z)4AdXeNv_SWR7kuBoE1}-HG1G6qnWAer+f!zL;&369C<|K!+^zFa4BoPtmkV3iF zQ(BqSO)6r3wSmd*%x=@4aJB2a#rzbE@&+iQ{R|4!LT0YNwbSoAM{oxJ9xPNZKtbPp z%w?(0Bx7=65BoY!Rwt0`vVXq&VZlqwuh-SpTg}?pYV-GSg-yDasXuWD0a)kuw zYiJcYPers6>b%SE`M +# Parameter : start_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# V0.2 : ama 02.2023 -- Adapted for Diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Diamond +# + +if ($verbose == 1) { + print "$separator\n\n"; + print "Launching Diamond from $designerExe\n"; + print $indent, "* Project file spec: $diamondFileSpec\n\n"; + print "$separator\n\n"; +} + +system("$designerExe $diamondFileSpec"); diff --git a/zz-solutions/01-WaveformGenerator/Scripts/start_libero.pl b/zz-solutions/01-WaveformGenerator/Scripts/start_libero.pl new file mode 100644 index 0000000..3e11301 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/start_libero.pl @@ -0,0 +1,37 @@ +#!/usr/bin/perl +# filename: start_libero.pl +# created by: Corthay Francois & Zahno Silvan +# +#------------------------------------------------------------------------------- +# +# Description: +# Starts Libero in the correct timezone for the Synplify License +# Help Parameter : +# Parameter : start_libero.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Libero +# + +if ($verbose == 1) { + print "\n"; + print "launching $designerExe\n"; + print $indent, "project file spec: $liberoFileSpec\n"; + print "$separator\n"; +} + +system("$designerExe $liberoFileSpec"); \ No newline at end of file diff --git a/zz-solutions/01-WaveformGenerator/Scripts/trimLibs.pl b/zz-solutions/01-WaveformGenerator/Scripts/trimLibs.pl new file mode 100644 index 0000000..efbff23 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/trimLibs.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ------------------------------------------------------------------------------ +# Changelog: +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/zz-solutions/01-WaveformGenerator/Scripts/update_diamond.pl b/zz-solutions/01-WaveformGenerator/Scripts/update_diamond.pl new file mode 100644 index 0000000..92e9076 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Scripts/update_diamond.pl @@ -0,0 +1,129 @@ +#!/usr/bin/perl +# filename: update_diamond.pl +# created by: Corthay Francois & Zahno Silvan & Amand Axel +# +#------------------------------------------------------------------------------- +# +# Description: +# Updates the file references in the .ldf Lattice project file +# and launches the Diamond project manager +# Help Parameter : +# Parameter : update_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# V0.3 : ama 02.2023 -- Adapted for diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$lpfFileSpec = $ARGV[2]; + +use File::Basename; +$diamond_dir = dirname(dirname($vhdlFileSpec)) . '/diamond/'; # get up concat and into diamond +$projectTitle = basename($diamondFileSpec, ".ldf"); + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * diamondFileSpec: $diamondFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * lpfFileSpec: $lpfFileSpec\n"; + print " * Project title: $projectTitle\n" +} + + +#------------------------------------------------------------------------------- +# Project variables +# + +$diamondWorkFileSpec = $diamondFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{DIAMOND_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n\n"; + print "Updating file specifications in $diamondFileSpec\n"; + print $indent, "temporary file spec: $diamondWorkFileSpec\n"; +} +my $line; +if ( !open(DiamondFile, $diamondFileSpec) ){ + print("\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"); + die "\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"; +} + +open(workFile, ">$diamondWorkFileSpec"); +while (chop($line = )) { + + # replace title + if ($line =~ m/ +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +# Parameter : update_libero.pl <^PDC File Spec> +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$pdcFileSpec = $ARGV[2]; + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * liberoFileSpec: $liberoFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * pdcFileSpec: $pdcFileSpec\n"; +} + + + +#------------------------------------------------------------------------------- +# Project variables +# +$liberoWorkFileSpec = $liberoFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{LIBERO_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $liberoFileSpec\n"; + print $indent, "temporary file spec: $liberoWorkFileSpec\n"; +} +my $line; + +open(LiberoFile, $liberoFileSpec) || die "couldn't open $HDLFileSpec!"; +open(workFile, ">$liberoWorkFileSpec"); +while (chop($line = )) { + # replace source path + if ($line =~ m/DEFAULT_IMPORT_LOC/i) { + $line =~ s/".*"/"$sourceDir"/; + } + # replace project path + if ($line =~ m/ProjectLocation/i) { + $line =~ s/".*"/"$projectDir"/; + } + # replace VHDL file spec + if ($line =~ m/VALUE\s".*,hdl"/i) { + $line =~ s/".*"/"$vhdlFileSpec,hdl"/; + } + # replace PDC file spec + if ($line =~ m/VALUE\s".*\.pdc,pdc"/i) { + $line =~ s/".*"/"$pdcFileSpec,pdc"/; + } + + print workFile ("$line\n"); +} + +close(workFile); +close(LiberoFile); + + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($liberoFileSpec); +rename($liberoWorkFileSpec, $liberoFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#------------------------------------------------------------------------------- +# Launch Libero +# + +#if ($verbose == 1) { +# print "\n"; +# print "launching $designerExe\n"; +# print $indent, "project file spec: $liberoFileSpec\n"; +# print "$separator\n"; +#} + +#system("$designerExe $liberoFileSpec"); diff --git a/zz-solutions/01-WaveformGenerator/Simulation/waveformGen.do b/zz-solutions/01-WaveformGenerator/Simulation/waveformGen.do new file mode 100644 index 0000000..ce4b33d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/Simulation/waveformGen.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /waveformgen_tb/reset +add wave -noupdate /waveformgen_tb/clock +add wave -noupdate /waveformgen_tb/en +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/triangle +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/polygon +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 272 +configure wave -valuecolwidth 89 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {525 us} +run 500 us diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg new file mode 100644 index 0000000..a0d98d6 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_entity.vhg @@ -0,0 +1,28 @@ +-- VHDL Entity WaveformGenerator.lowpass.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lowpass IS + GENERIC( + signalBitNb : positive := 16; + shiftBitNb : positive := 12 + ); + PORT( + lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END lowpass ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_masterVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_masterVersion.vhd new file mode 100644 index 0000000..0adecd0 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_masterVersion.vhd @@ -0,0 +1,19 @@ +ARCHITECTURE masterVersion OF lowpass IS + + constant additionalBitNb: positive := shiftBitNb; + signal lowpassReg: unsigned(lowpassIn'length+additionalBitNb-1 downto 0); + +begin + + filter: process(reset, clock) + begin + if reset = '1' then + lowpassReg <= (others => '0'); + elsif rising_edge(clock) then + lowpassReg <= lowpassReg + lowpassIn - shift_right(lowpassReg, shiftBitNb); + end if; + end process filter; + + lowpassOut <= lowpassReg(lowpassReg'high downto lowpassReg'high-lowpassOut'length+1); + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd new file mode 100644 index 0000000..f2e46c5 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/lowpass_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF lowpass IS +BEGIN + lowpassOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_masterVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_masterVersion.vhd new file mode 100644 index 0000000..b072504 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_masterVersion.vhd @@ -0,0 +1,21 @@ +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd new file mode 100644 index 0000000..892bd7d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE studentVersion OF sawtoothGen IS +BEGIN + sawtooth <= (others => '0'); +END ARCHITECTURE studentVersion; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_masterVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_masterVersion.vhd new file mode 100644 index 0000000..c019913 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_masterVersion.vhd @@ -0,0 +1,6 @@ +ARCHITECTURE masterVersion OF sawtoothToSquare IS +BEGIN + + square <= (others => sawtooth(sawtooth'high)); + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd new file mode 100644 index 0000000..f8b09bd --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF sawtoothToSquare IS +BEGIN + square <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_masterVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_masterVersion.vhd new file mode 100644 index 0000000..64b4708 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_masterVersion.vhd @@ -0,0 +1,21 @@ +ARCHITECTURE masterVersion OF sawtoothToTriangle IS + + signal MSB: std_uLogic; + signal triangleInt: unsigned(triangle'range); + +begin + + MSB <= sawtooth(sawtooth'high); + + foldDown: process(MSB, sawtooth) + begin + if MSB = '0' then + triangleInt <= sawtooth; + else + triangleInt <= not sawtooth; + end if; + end process foldDown; + + triangle <= triangleInt(triangleInt'high-1 downto 0) & '0'; + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd new file mode 100644 index 0000000..9fa87cc --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF sawtoothToTriangle IS +BEGIN + triangle <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothgen_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothgen_entity.vhg new file mode 100644 index 0000000..3f707ec --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothgen_entity.vhg @@ -0,0 +1,28 @@ +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtosquare_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtosquare_entity.vhg new file mode 100644 index 0000000..a81570f --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtosquare_entity.vhg @@ -0,0 +1,25 @@ +-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToSquare IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToSquare ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtotriangle_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtotriangle_entity.vhg new file mode 100644 index 0000000..08c91f4 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothtotriangle_entity.vhg @@ -0,0 +1,25 @@ +-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToTriangle IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToTriangle ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_masterVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_masterVersion.vhd new file mode 100644 index 0000000..3e6228c --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_masterVersion.vhd @@ -0,0 +1,26 @@ +ARCHITECTURE masterVersion OF triangleToPolygon IS + + constant clipLow: positive := 2**(triangle'length-2); + constant clipHigh: positive := 5*clipLow; + + signal triangleGain: unsigned(triangle'length downto 0); + +begin + + gain_1_5: process(triangle) + begin + triangleGain <= ("0" & triangle) + ( "00" & triangle(triangle'high downto 1) ); + end process gain_1_5; + + clip: process(triangleGain) + begin + if triangleGain < clipLow then + polygon <= (others => '0'); + elsif triangleGain > clipHigh then + polygon <= (others => '1'); + else + polygon <= triangleGain(polygon'range) - clipLow; + end if; + end process clip; + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd new file mode 100644 index 0000000..0cb1a55 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF triangleToPolygon IS +BEGIN + polygon <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangletopolygon_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangletopolygon_entity.vhg new file mode 100644 index 0000000..43f0c74 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/triangletopolygon_entity.vhg @@ -0,0 +1,25 @@ +-- VHDL Entity WaveformGenerator.triangleToPolygon.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY triangleToPolygon IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + polygon : OUT unsigned (bitNb-1 DOWNTO 0); + triangle : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END triangleToPolygon ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_entity.vhg new file mode 100644 index 0000000..e7a416e --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_entity.vhg @@ -0,0 +1,33 @@ +-- VHDL Entity WaveformGenerator.waveformGen.symbol +-- +-- Created: +-- by - francois.corthay.UNKNOWN (WEA20303) +-- at - 17:19:13 06.03.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY waveformGen IS + GENERIC( + phaseBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + en : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + polygon : OUT unsigned (signalBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END waveformGen ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg new file mode 100644 index 0000000..f59d795 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hdl/waveformgen_struct.vhg @@ -0,0 +1,146 @@ +-- +-- VHDL Architecture WaveformGenerator.waveformGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:40:08 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF waveformGen IS + + -- Architecture declarations + + -- Internal signal declarations + + -- Implicit buffer signal declarations + SIGNAL polygon_internal : unsigned (signalBitNb-1 DOWNTO 0); + SIGNAL sawtooth_internal : unsigned (phaseBitNb-1 DOWNTO 0); + SIGNAL triangle_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT lowpass + GENERIC ( + signalBitNb : positive := 16; + shiftBitNb : positive := 12 + ); + PORT ( + lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT triangleToPolygon + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + polygon : OUT unsigned (bitNb-1 DOWNTO 0); + triangle : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass; + FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; + FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; + FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; + FOR ALL : triangleToPolygon USE ENTITY WaveformGenerator.triangleToPolygon; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_lp : lowpass + GENERIC MAP ( + signalBitNb => signalBitNb, + shiftBitNb => 10 + ) + PORT MAP ( + lowpassOut => sine, + clock => clock, + reset => reset, + lowpassIn => polygon_internal + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => sawtooth_internal, + clock => clock, + reset => reset, + step => step, + en => en + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle_internal, + sawtooth => sawtooth_internal + ); + I_poly : triangleToPolygon + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + polygon => polygon_internal, + triangle => triangle_internal + ); + + -- Implicit buffered output assignments + polygon <= polygon_internal; + sawtooth <= sawtooth_internal; + triangle <= triangle_internal; + +END struct; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.cache.dat b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.cache.dat new file mode 100644 index 0000000000000000000000000000000000000000..819f9f9b595ded95d3030dba9d21c1593d132acf GIT binary patch literal 5487 zcmcgw&2Q5%6!*IBi&p#SKtp_tO54ylQ0N3mAP`$=wN-44ZPmt3QQC&CD6L15ZYl`z zHz0B4f`kM&j@&qLKpYTfZiqVvB+k5-#%Y!~R;PMJ z8miGumekUYMnJ~quBLCM=906SMpZ8-uV2E(#Fo0JJ*Gx&QLAf)YEc7Qdz{NIoW>TA zgiiN&Rnxp;Hfu$yr_3U@#UkQnPg!0H@?m=#Sp^(cen@ia)xXv)Hnrd2_v8fqmmDYi> z+@iFn6}bhK6G)^Ka*qo38@z$I)97esXBnGmHOeqMJ{{QuU>S51rn+xYYVFKdv^sae zwm$(?*9&&u<+13z`Lv-L8kcQtN(S2nFPmjl)p|t_;kzS)&($I*F=&!Q|G*^Q0*^G4 zoMiI@XH-OH+4BZyW!QI+H46Z=k9)Y?8R zqfxR_MQ>v8`xj6RXO>s*-B+^tg~j!S6=)zayn!4pIq=bO(yJ%40NS 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b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_masterVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_masterVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_masterVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_masterVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_masterVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/lowpass_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/lowpass_entity.xrf new file mode 100644 index 0000000..daaa156 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/lowpass_entity.xrf @@ -0,0 +1,27 @@ +DESIGN lowpass +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 57,0 18 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 52,0 19 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 76,0 20 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 83,0 21 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 1,0 24 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 1,0 25 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothgen_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothgen_entity.xrf new file mode 100644 index 0000000..b4cebc4 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothgen_entity.xrf @@ -0,0 +1,30 @@ +DESIGN sawtooth@gen +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 57,0 17 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 52,0 18 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 76,0 19 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 83,0 20 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 89,0 21 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 1,0 24 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 1,0 25 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtosquare_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtosquare_entity.xrf new file mode 100644 index 0000000..c726488 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtosquare_entity.xrf @@ -0,0 +1,21 @@ +DESIGN sawtooth@to@square +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 57,0 17 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 83,0 18 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 1,0 21 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 1,0 22 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtotriangle_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtotriangle_entity.xrf new file mode 100644 index 0000000..52c935d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/sawtoothtotriangle_entity.xrf @@ -0,0 +1,21 @@ +DESIGN sawtooth@to@triangle +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 57,0 17 0 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 83,0 18 0 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 1,0 21 0 +DESIGN sawtooth@to@triangle +VIEW symbol.sb +GRAPHIC 1,0 22 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/triangletopolygon_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/triangletopolygon_entity.xrf new file mode 100644 index 0000000..911ab55 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/triangletopolygon_entity.xrf @@ -0,0 +1,21 @@ +DESIGN triangle@to@polygon +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 57,0 17 0 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 83,0 18 0 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 1,0 21 0 +DESIGN triangle@to@polygon +VIEW symbol.sb +GRAPHIC 1,0 22 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_entity.xrf new file mode 100644 index 0000000..02015c0 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_entity.xrf @@ -0,0 +1,42 @@ +DESIGN waveform@gen +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 52,0 18 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 123,0 19 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 88,0 20 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 113,0 21 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 93,0 22 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 98,0 23 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 103,0 24 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 108,0 25 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 118,0 26 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 1,0 29 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 1,0 30 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_struct.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_struct.xrf new file mode 100644 index 0000000..69bfc82 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/.xrf/waveformgen_struct.xrf @@ -0,0 +1,215 @@ +DESIGN waveform@gen +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 84,0 9 0 +DESIGN waveform@gen +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN waveform@gen +VIEW struct.bd +NO_GRAPHIC 20 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 513,0 22 0 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 414,0 23 0 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 424,0 24 0 +DESIGN waveform@gen +VIEW struct.bd +NO_GRAPHIC 26 +LIBRARY WaveformGenerator +DESIGN lowpass +VIEW master@version +GRAPHIC 1036,0 28 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 14,0 29 1 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 57,0 34 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 52,0 35 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 76,0 36 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 83,0 37 0 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 1227,0 40 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 14,0 41 1 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 57,0 45 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 52,0 46 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 76,0 47 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 83,0 48 0 +DESIGN sawtooth@gen +VIEW symbol.sb +GRAPHIC 89,0 49 0 +DESIGN waveform@gen +VIEW struct.bd +GRAPHIC 916,0 52 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 14,0 53 1 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 57,0 57 0 +DESIGN sawtooth@to@square +VIEW symbol.sb +GRAPHIC 83,0 58 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masterVersion +DEFAULT_FILE atom lowpass_masterVersion.vhd diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf new file mode 100644 index 0000000..fad87d6 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom sawtoothGen_masterVersion.vhd +DEFAULT_ARCHITECTURE atom masterVersion diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf new file mode 100644 index 0000000..55351fb --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom sawtoothToSquare_masterVersion.vhd diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf new file mode 100644 index 0000000..c8d1748 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom sawtoothToTriangle_masterVersion.vhd diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf new file mode 100644 index 0000000..7f86fe2 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom triangleToPolygon_masterVersion.vhd diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_waveformgen._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator/hds/_waveformgen._epf new file mode 100644 index 0000000..c91c6be --- /dev/null +++ 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waveformGen_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + +begin + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- enable + en <= '0', '1' after 100 us; + + ------------------------------------------------------------------------------ + -- frequency control + step <= to_unsigned(2**(step'length-13), step'length); + +END ARCHITECTURE test; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg new file mode 100644 index 0000000..6ec26bf --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity WaveformGenerator_test.waveformGen_tb.symbol +-- +-- Created: +-- by - francois.corthay.UNKNOWN (WEA30906) +-- at - 14:48:16 25.02.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY waveformGen_tb IS +-- Declarations + +END waveformGen_tb ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg new file mode 100644 index 0000000..b264994 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg @@ -0,0 +1,100 @@ +-- +-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:39:46 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY WaveformGenerator; +LIBRARY WaveformGenerator_test; + +ARCHITECTURE struct OF waveformGen_tb IS + + -- Architecture declarations + constant bitNb: positive := 16; + constant clockFrequency: real := 60.0E6; + --constant clockFrequency: real := 66.0E6; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL en : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL step : unsigned(bitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT waveformGen + GENERIC ( + phaseBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + en : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + polygon : OUT unsigned (signalBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT waveformGen_tester + GENERIC ( + bitNb : positive := 16; + clockFrequency : real := 60.0E6 + ); + PORT ( + clock : OUT std_ulogic ; + en : OUT std_ulogic ; + reset : OUT std_ulogic ; + step : OUT unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen; + FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_DUT : waveformGen + GENERIC MAP ( + phaseBitNb => bitNb, + signalBitNb => bitNb + ) + PORT MAP ( + clock => clock, + en => en, + reset => reset, + step => step, + polygon => OPEN, + sawtooth => OPEN, + sine => OPEN, + square => OPEN, + triangle => OPEN + ); + I_tb : waveformGen_tester + GENERIC MAP ( + bitNb => bitNb, + clockFrequency => clockFrequency + ) + PORT MAP ( + clock => clock, + en => en, + reset => reset, + step => step + ); + +END struct; diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg new file mode 100644 index 0000000..0a4e2a9 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg @@ -0,0 +1,28 @@ +-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:39:31 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +ENTITY waveformGen_tester IS + GENERIC( + bitNb : positive := 16; + clockFrequency : real := 60.0E6 + ); + PORT( + clock : OUT std_ulogic; + en : OUT std_ulogic; + reset : OUT std_ulogic; + step : OUT unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END waveformGen_tester ; + diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.cache.dat b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.cache.dat new file mode 100644 index 0000000000000000000000000000000000000000..ee0c2c3cc88a322ee489976233755e8d07f8192e GIT binary patch literal 1636 zcmcgsOHbQC5MBZy5vt-`6TT_CK9`~=@oFqwWMuFJM&*4#yDlR^p=#W zx|AgqcQn(b6~hRNLoy$OQe_Z_^U9}UcV!JKme8iT8+j8 zZRA%#JU~f^H4{t(BGfSB<{cs;nux*(C#zgPrmkQ#bEm_v7Q&|^WyF0vZa5hK1u9*I zXY1+u56@phQ%0PQ-GH+Ma60;y2JuWHbwtQtWdEF*&?5B>Kl>I(8yGyxNm2go3sG6H H&<}eA25uQN literal 0 HcmV?d00001 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_entity.xrf new file mode 100644 index 0000000..2a08512 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_entity.xrf @@ -0,0 +1,12 @@ +DESIGN waveform@gen_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN waveform@gen_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN waveform@gen_tb +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN waveform@gen_tb +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf new file mode 100644 index 0000000..57ec1ce --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tb_struct.xrf @@ -0,0 +1,132 @@ +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 0,0 16 2 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 1,0 19 0 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 19 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 53,0 24 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 700,0 25 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 45,0 26 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 594,0 27 0 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 28 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 29 +LIBRARY WaveformGenerator +DESIGN waveform@gen +VIEW struct +GRAPHIC 954,0 31 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 14,0 32 1 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 52,0 37 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 123,0 38 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 88,0 39 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 113,0 40 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 93,0 41 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 98,0 42 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 103,0 43 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 108,0 44 0 +DESIGN waveform@gen +VIEW symbol.sb +GRAPHIC 118,0 45 0 +LIBRARY WaveformGenerator_test +DESIGN waveform@gen_tester +VIEW test +GRAPHIC 421,0 48 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 14,0 49 1 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 55,0 54 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 702,0 55 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 47,0 56 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 596,0 57 0 +LIBRARY WaveformGenerator_test +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 60 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 954,0 63 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 421,0 64 0 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 67 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 69 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 954,0 71 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 961,0 72 1 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 55,0 77 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 702,0 78 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 47,0 79 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 596,0 80 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 421,0 87 0 +DESIGN waveform@gen_tb +VIEW struct.bd +GRAPHIC 428,0 88 1 +DESIGN waveform@gen_tb +VIEW struct.bd +NO_GRAPHIC 99 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf new file mode 100644 index 0000000..f682bca --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/.xrf/waveformgen_tester_entity.xrf @@ -0,0 +1,27 @@ +DESIGN waveform@gen_tester +VIEW interface +NO_GRAPHIC 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 18,0 8 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 13,0 13 1 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 636,0 18 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 641,0 19 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 646,0 20 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 651,0 21 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 1,0 24 0 +DESIGN waveform@gen_tester +VIEW interface +GRAPHIC 1,0 25 0 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf new file mode 100644 index 0000000..25a3e3e --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom waveform@gen_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf b/zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf new file mode 100644 index 0000000..f982b8b --- /dev/null +++ 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(CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *73 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,5200,44400,6200" +st "User:" +blo "42000,6000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6200,44000,6200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 663,0 +activeModelName "Symbol:GEN" +) diff --git a/zz-solutions/01-WaveformGenerator/waveformGenerator.bash b/zz-solutions/01-WaveformGenerator/waveformGenerator.bash new file mode 100644 index 0000000..933ab09 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/waveformGenerator.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/zz-solutions/01-WaveformGenerator/waveformGenerator.bat b/zz-solutions/01-WaveformGenerator/waveformGenerator.bat new file mode 100644 index 0000000..bc1b2a4 --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/waveformGenerator.bat @@ -0,0 +1,83 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +set HDS_HOME=C:\MentorGraphics\HDS_2019.2 +set MODELSIM_HOME=C:\modeltech64_2021.3\win64 +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +set LM_LICENSE_FILE=27001@mentorlm.hevs.ch + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/01-WaveformGenerator/waveformGenerator.bat.bak b/zz-solutions/01-WaveformGenerator/waveformGenerator.bat.bak new file mode 100644 index 0000000..643473d --- /dev/null +++ b/zz-solutions/01-WaveformGenerator/waveformGenerator.bat.bak @@ -0,0 +1,81 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +set HDS_HOME=C:\MentorGraphics\HDS_2019.2 +set MODELSIM_HOME=C:\modeltech64_2021.3\win64 +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds.hdp b/zz-solutions/02-SplineInterpolator/Prefs/hds.hdp new file mode 100644 index 0000000..3a75d9b --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds.hdp @@ -0,0 +1,25 @@ +[Concat] +[ModelSim] +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/shared.hdp b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs.bak b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs.bak new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs.bak @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st 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+RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape 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+visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..0a7d5eb --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6092 @@ +version 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"$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair 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+cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..3d39e11 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/sineGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension 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"Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name 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"Standard Delay File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) 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"$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Sublime Text" +second "sublime_text.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l) -ro" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 4 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "$TEMP" +projectPaths [ +"hds.hdp" +"D:\\Labs\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\Users\\oliver.gubler\\eda\\VHDL\\labs\\ELN_cursor\\Prefs\\hds.hdp" +"R:\\SYND\\Ele_2131\\ELN\\Labs\\Cursor\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\work\\git\\Education\\Projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\eln_labs.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +" +defaultVerilogPackages "" +defaultFont "Verdana,9,0" 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+displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Top Marker" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Size" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "H(A(C(LogicalObjects),C(Files),C(DesignUnits)),A(C(DesignHierarchy)))" +) +(Viewpoint_v2 +name "All Views" +TreeListVPDatas [ +(TreeListVPData +theList "Design Units" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Top Marker" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Size" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(H(A(C(DesignUnits)),A(C(Files))),H(A(C(DesignHierarchy)),A(C(LogicalObjects))))" +) +(Viewpoint_v2 +name "Requirements" +TreeListVPDatas [ +(TreeListVPData +theList "Design Units" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Top Marker" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Size" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +(SmartTableVPData_Column +name "Requirement References" +width -1 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" +) +] +WorkTabs [ +(WorkTab +name "Cursor" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor" +primaryName "cursorCircuit" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Cursor_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor_test" +primaryName "cursor_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Board" +primaryName "FPGA_cursor" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "LCD" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 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+gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" 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+vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..8d78b3f --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6843 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" 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%(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl 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"uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l) -ro" +) +(pair +first "Sublime Text" +second "sublime_text.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +defaultVerilogDialect 5 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+"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\Users\\andrea.guerrier\\Documents\\SEm_labs\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +" +defaultVerilogPackages "" +defaultFont "Verdana,9,0" +tableFont "Tahoma,10,0" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN" +pageSizes [ +(PageSizeInfo +name "12\" x 18\"" +type 512 +width 1106 +height 1658 +) +(PageSizeInfo +name "11\" x 17\"" +type 17 +width 1013 +height 1566 +) +(PageSizeInfo +name "Legal (8,5\" x 14\")" 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[ +"hds.hdp" +"D:\\Labs\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\Users\\oliver.gubler\\eda\\VHDL\\labs\\ELN_cursor\\Prefs\\hds.hdp" +"R:\\SYND\\Ele_2131\\ELN\\Labs\\Cursor\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\work\\git\\Education\\Projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\eln_labs.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\hds.hdp" +"C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\01-WaveformGenerator\\Prefs\\hds.hdp" +"C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +projectSetupRootDir "" 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+processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet 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"Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..3d39e11 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/sineGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/02-SplineInterpolator/Scripts/.gitlab-ci.yml b/zz-solutions/02-SplineInterpolator/Scripts/.gitlab-ci.yml new file mode 100644 index 0000000..9d1d7af --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/.gitlab-ci.yml @@ -0,0 +1,53 @@ +stages: + - deploy + +image: alpine:latest + +scripts: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployScriptsAll.bash + - deployScripts.bash + - /*.{pl} + - when: manual + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Bash" + - apk add bash + - echo "Install Core Utils" + - apk add coreutils + - echo "Install Git" + - apk add git + - echo "Set Git credentials" + - git config --global user.email "silvan.zahno@hevs.ch" + - git config --global user.name "Silvan Zahno" + - echo "Setting up deploy-eda_scripts environment" + + script: + - bash ./deployScriptsAll.bash + +libs_trigger: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployLibsAll.bash + - deployLibs.bash + - when: manual + variables: + GIT_CHECKOUT: "false" + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Curl" + - apk add curl + + script: + - 'curl -X POST --fail -F token=glptt-0235c37f03e3060733df7d1151555fd0c63d0adb -F ref=master "https://gitlab.hevs.ch/api/v4/projects/762/trigger/pipeline"' diff --git a/zz-solutions/02-SplineInterpolator/Scripts/LICENSE b/zz-solutions/02-SplineInterpolator/Scripts/LICENSE new file mode 100644 index 0000000..fdf8bfa --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/LICENSE @@ -0,0 +1,11 @@ +All Rights Reserved + +Copyright (c) 2019 - HES-SO Valais Wallis + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/README.md b/zz-solutions/02-SplineInterpolator/Scripts/README.md new file mode 100644 index 0000000..618a38f --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/README.md @@ -0,0 +1,238 @@ +

+
+ EDA scripts Logo +
+ Hevs EDA Scripts +
+

+ +

Common Files and Scripts for ELN Laboratories practical sessions.

+ +[![pipeline status](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/pipeline.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) +[![coverage report](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/coverage.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) + +# Table of contents + + +## Description +[(Back to top)](#table-of-contents) + +These scripts can be used as for: +**Git Repos** +* [EDA_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +* [ELN_labs](https://gitlab.hevs.ch/course/ElN/eln_labs.git) +* [SEm_exams](https://gitlab.hevs.ch/course/SEm/exams.git) +* [ELN_chrono](https://gitlab.hevs.ch/course/ElN/eln_chrono.git) +* [ELN_cursor](https://gitlab.hevs.ch/course/ElN/eln_cursor.git) +* [ELN_kart](https://gitlab.hevs.ch/course/ElN/eln_kart.git) +* [ELN_inverter](https://gitlab.hevs.ch/course/ElN/eln_inverter.git) +* [ELN_synchro](https://gitlab.hevs.ch/course/ElN/eln_synchro.git) +* [SEm_labs](https://gitlab.hevs.ch/course/SEm/sem_labs.git) +* [ELN-kart](https://gitlab.hevs.ch/course/ElN/eln_kart_sodimm200.git) +* [ELN-display](https://gitlab.hevs.ch/course/ElN/eln_display.git) + +**SVN Repos** +* [CanSat](https://repos.hevs.ch/svn/eda/VHDL/labs/CanSat) (TODO) :rotating_light: +* [ELN_support](https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_support) (TODO) :rotating_light: +* [EPTM_AudioAmp](https://repos.hevs.ch/svn/eda/VHDL/labs/AudioAmp) (TODO) :rotating_light: +* [EPTM_Radio](https://repos.hevs.ch/svn/eda/VHDL/labs/EPTM_radio) (TODO) :rotating_light: +* ... + +### Files +**Linux** +* ``changeDefaultViews.bash`` - Changes RTL <=> studentVersion + * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` + * Usage master => student: ``changeDefaultViews.bash -v -a master@version -n student@version`` + * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` + * Usage student => master: ``changeDefaultViews.bash -v -a student@version -n master@version`` + * Note: use the ``-r`` otion to also delete the specified actual_view +* ``cleanGenerated.bash`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bash`` +* ``hdlDesigner.bash`` - Main script for starting HDL-Designer +* ``deployLibs.bash`` - Execution from eln_libs repo, copy required libraries to student repo and commit/push it. + * Usage: ``./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployLibsAll.bash`` - Execution from eln_libs repo, copy required libraries to all student repo's and commit/push it. + * Usage: ``./Scripts/deployLibsAll.bash`` +* ``deployLab.bash`` - Execution from Laborepo, copy required laboratory files to student repo and commits/push it. + * Usage: ``./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScripts.bash`` - Copy required scripts to student repo and commits/push it. + * Usage: ``./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScriptsAll.bash`` - Execution from eln_scripts repo, copy required scripts to all student repo's and commit/push it. + * Usage: ``./deployScriptsAll.bash`` + +**Windows** +* ``cleanGenerated.bat`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bat`` +* ``cleanScratch.bat`` - Delete scratch directory + * Usage: +``` bash +set SCRATCH_DIR=C:\temp\eda\%username% +./cleanScratch.bat +``` + +* ``hdlDesigner.bat`` - Main script for starting HDL-Designer +* ``searchPaths.bat`` - Search for required Libraries and tools + * Usage: +``` bash +:: Define required Tools to be present +set REQUIRE_LIBS=1 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=1 +set REQUIRE_LIBERO=0 +set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries +set HDS_HOME=C:\eda\MentorGraphics\HDS +set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +set ISE_VERSION=14.7 +set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +set LIBERO_HOME=C:\eda\Microsemi\Libero +set design_name=eln_labs +./searchPaths.bat +``` + +**Perl Scripts** +Perl scripts are used to launch different tasks from HDL-Designer +* ``trimLibs.pl`` - Comment regular libraries in an concatenated file + * Parameter : ``trimlibs.pl `` +* ``update_ise.pl`` - + * Parameter : ``update_ise.pl `` +* ``update_libero.pl`` - + * Parameter : ``update_libero.pl `` +* ``start_libero.pl`` - + * Parameter : ``start_libero.pl `` + +## How To Use +[(Back to top)](#table-of-contents) + +To clone and run this application, you'll need [Git](https://git-scm.com) installed on your computer. +This repo is normally used as submodule to the laboratories and projects. + +To deploy the studentVersion to github cd to root of Labor master repo: +```bash +cd eln_labs +./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLab.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLab.bash -v -p isc-eln-labs -r https://github.com/hei-isc-eln/eln-labs.git + +cd sem_labs +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 01-WaveformGenerator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 02-SplineInterpolator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 03-DigitalToAnalogConverter +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 04-Lissajous +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 05-Morse +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 06-07-08-09-SystemOnChip +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 10-PipelinedOperators + +cd eln_chrono +./Scripts/deployLab.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git + +cd eln_cursor +./Scripts/deployLab.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git + +cd eln-display +./Scripts/deployLab.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git + +cd eln-kart +./Scripts/deployLab.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +``` + +To deploy the Libraries to github cd to root of Libs master repo: +```bash +./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./Scripts/deployLibs.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./Scripts/deployLibs.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./Scripts/deployLibs.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./Scripts/deployLibs.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./Scripts/deployLibs.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./Scripts/deployLibs.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./Scripts/deployLibs.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +./Scripts/deployLibs.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./Scripts/deployLibsAll.bash +``` + +To deploy the Scripts to github cd root of Scripts master Repo +```bash +./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./deployScripts.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./deployScripts.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./deployScripts.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./deployScripts.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./deployScripts.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./deployScripts.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./deployScripts.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./deployScripts.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./deployScripts.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-display.git +./deployScripts.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./deployScriptsAll.bash +``` + +
+![eln labs deployment](img/eln_labs_deployment-staff.png) +
+ +### Download +```bash +# Clone repo including submodules +git clone --recursive +``` + +### Pull changes repo and submodules +```bash +# Pull all changes in the repo including changes in the submodules (of given commit) +git pull --recurse-submodules +``` + +#### Update to latest commit +Update submodule to latest commit and update parentrepo +```bash +# Update submodule to latest commit +git submodule update --remote --merge + +# Afterwared you need to commit in the parentrepo the new pointer to the new commit in the submodule +git commit -am "Update submodule to latest commit" +``` + +### Add submodule +If the folder ``Scripts`` already exists, delete it and commit these changes. +Add submodule and define the master branch as the one you want to track +```bash +git submodule add -b master +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_scripts.git Scripts +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_libs.git Libs + +git submodule init + +git submodule update +``` + +## Credits +[(Back to top)](#table-of-contents) +* COF +* PRC +* ZAS +* AMA + +## License +[(Back to top)](#table-of-contents) + +:copyright: [All rights reserved](LICENSE) + +--- + +## Find us on +> Website [hevs.ch](https://www.hevs.ch)  ·  +> LinkedIn [HES-SO Valais-Wallis](https://www.linkedin.com/groups/104343/)  ·  +> Youtube [HES-SO Valais-Wallis](https://www.youtube.com/user/HESSOVS) +> Twitter [@hessovalais](https://twitter.com/hessovalais)  ·  +> Facebook [@hessovalais](https://www.facebook.com/hessovalais)  ·  \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/changeDefaultViews.bash b/zz-solutions/02-SplineInterpolator/Scripts/changeDefaultViews.bash new file mode 100644 index 0000000..be6fa62 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/changeDefaultViews.bash @@ -0,0 +1,94 @@ +#!/bin/bash + +#================================================================================ +# changeDefaultViews.bash - change HDL Project views +# * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` +# * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` +# * Usage: add ``-r`` for deleting the specified actual view **dangerous** +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +project_directory='' +actual_view='masterVersion' +new_view='studentVersion' + +usage='Usage: changeDefaultViews.bash [-p projectDir] [-r] [-v] [-h]' +while getopts 'p:a:n:rvh' options; do + case $options in + p ) project_directory=$OPTARG;; + a ) actual_view=$OPTARG;; + n ) new_view=$OPTARG;; + r ) delete_actual_view=1;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done +if [ -z "$project_directory" ]; then + project_directory="$base_directory" +else + project_directory="$base_directory/$project_directory" +fi + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Changing default views for HDL Designer" + echo "${INDENT}in $project_directory" + echo "${INDENT}from $actual_view to $new_view" + if [ -n "$delete_actual_view" ] ; then + echo "Delete all $actual_view in $project_directory" + fi +fi + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Change views in configuration files +# +find $project_directory -type f -name '*._epf' \ + | xargs sed -i "s/$actual_view/$new_view/g" + +#------------------------------------------------------------------------------- +# Remove all acutal views File +# +if [ -n "$delete_actual_view" ] ; then + project_directory=`realpath $project_directory` + echo $project_directory + echo "Delete $actual_view" + find $project_directory/ -type f -iname "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -iname "*$actual_view*" -exec rm {} \; + # For HDL Designer file naming convention + # making uppercase letters to @lowercase masterVersion = master@version + actual_view="$(sed -E s/\([A-Z]\)/@\\L\\1/g <<< $actual_view)" + find $project_directory/ -type f -name "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -name "*$actual_view*" -exec rm {} \; + +fi + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bash b/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bash new file mode 100644 index 0000000..ca088c6 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bat b/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/cleanScratch.bat b/zz-solutions/02-SplineInterpolator/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deployLab.bash b/zz-solutions/02-SplineInterpolator/Scripts/deployLab.bash new file mode 100644 index 0000000..10652b0 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deployLab.bash @@ -0,0 +1,559 @@ +#!/bin/bash + +#================================================================================ +# deployLab.bash - updates github repos for individual labos +# Example usage 01: ./Scripts/deployLab.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 02: ./Scripts/deployLab.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 03: ./Scripts/deployLab.bash -v -p isc-did-labs -r https://github.com/hei-isc-eln/did-labs.git +# Example usage 04: ./Scripts/deployLab.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 05: ./Scripts/deployLab.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 06: ./Scripts/deployLab.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 07: ./Scripts/deployLab.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 08: ./Scripts/deployLab.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 09: ./Scripts/deployLab.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git + +# Example usage 10: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 11: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 12: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +# Example usage 13: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +# Example usage 14: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +# Example usage 15: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +# Example usage 16: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +# Example usage 17: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +# Example usage 18: ./Scripts/deployLab.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -s 1 +# Example usage 19: ./Scripts/deployLab.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='synd-did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +dir='01-StepperMotor' +sourceDirUp=0 + +usage='Usage: deployLab.bash [-p projectName] [-r repourl] [-d directory] [-s sourceDirUp] [-v] [-h]' +while getopts 'p:r:d:s:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) dir=$OPTARG;; + s ) sourceDirUp=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Laboratory for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "${INDENT}in $dir" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +repo_dest=`realpath "./"` +repo_source="./" +# If Scripts folder is at root of project, needs to get up 3 times (scripts, project name, tmp) +# If more is needed (i.e. see car-labs structure), can be added with -s switch +for ((i=0;i<$sourceDirUp+3;i++)); do + repo_source="$repo_source/.." +done +repo_source=`realpath "$repo_source"` + +echo "Update files in student repo $project" +# Copy needed files per project +if [ "$project" == "synd-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "ete-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "isc-did-labs" ]; then + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "car-labs" ]; then + # bem + echo "copy $repo_source/bem" + cp -ar "$repo_source/bem" ./ + # isa + echo "copy $repo_source/isa" + cp -ar "$repo_source/isa" ./ + # heirv32_sc + mkdir -p heirv32_sc + # copy root files except some specific ones + find $repo_source/hdl -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest/heirv32_sc \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source/hdl -maxdepth 1 -type d ) + do + if [[ "$repo_source/hdl" != "$folder" && "$repo_source/hdl/.git" != "$folder" && "$repo_source/hdl/Libs" != "$folder" && "$repo_source/hdl/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder heirv32_sc/ + else + echo "skip $folder" + fi + done + + rm -v -f heirv32_sc/Board/concat/concatenated.vhd + rm -v -f heirv32_sc/Board/concat/car-labs.vhd + + rm -v -f heirv32_sc/HEIRV32/hdl/ALU_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/extend_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/hds/alu@decoder + rm -v -f heirv32_sc/HEIRV32/hds/_aludecoder._epf + + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/SingleCycle/hds/main@decoder + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hds/_maindecoder._epf + + rm -v -f heirv32_sc/Simulation/empty_ram.txt + +elif [ "$project" == "car-heirv" ]; then + # heirv32_mc + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source/" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + + rm -v -f ./Board/concat/concatenated.vhd + rm -v -f ./Board/concat/car-labs.vhd + + rm -v -f ./HEIRV32/hdl/ALU_rtl.vhd + rm -v -f ./HEIRV32/hdl/extend_rtl.vhd + rm -v -f ./HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f ./HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r ./HEIRV32/hds/alu@decoder + rm -v -f ./HEIRV32/hds/_aludecoder._epf + + rm -v -f ./HEIRV32/MultiCycle/hdl/instrdecoder_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_fsm.vhg + rm -v -f -r ./HEIRV32/MultiCycle/hds/instr@decoder + rm -v -f -r ./HEIRV32/MultiCycle/hds/main@f@s@m + rm -v -f ./HEIRV32/MultiCycle/hds/_instrdecoder._epf + rm -v -f ./HEIRV32/MultiCycle/hds/_mainfsm._epf + + rm -v -f ./HEIRV32_test/hdl/universalTester_test.vhd + rm -v -f -r ./HEIRV32_test/hds/universal@tester + rm -v -f ./HEIRV32_test/hds/_universaltester._epf + + rm -v -f ./Simulation/code_mc_disassembled.svg + rm -v -f ./Simulation/code_mc_disassembled_labels.svg + rm -v -f ./Simulation/code_mc_ghidra_labels.png + rm -v -f ./Simulation/empty_ram.txt + + #search='design_root = Board.ebs2_sc(struct)ebs2_sc/struct.bd' + #replace='design_root = Board.ebs2_mc(struct)ebs2_mc/struct.bd' + #sed -i "s/$search/$replace" Prefs/hds.hdp + +elif [ "$project" == "ele_labs" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "sem-labs" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/01-WaveformGenerator/Scripts" != "$folder" && "$repo_source/02-SplineInterpolator/Scripts" != "$folder" && "$repo_source/03-DigitalToAnalogConverter/Scripts" != "$folder" && "$repo_source/04-Lissajous/Scripts" != "$folder" && "$repo_source/05-Morse/Scripts" != "$folder" && "$repo_source/06-07-08-09-SystemOnChip/Scripts" != "$folder" && "$repo_source/10-PipelinedOperators/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for sem-labs $dir" + + if [ "$dir" == "01-WaveformGenerator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "02-SplineInterpolator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "03-DigitalToAnalogConverter" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "04-Lissajous" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "05-Morse" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "06-07-08-09-SystemOnChip" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "10-PipelinedOperators" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-cursor" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-cursor" + rm -v -f ./Cursor/hdl/amplitudeControl_RTL.vhd + rm -v -f ./Cursor/hdl/bridgeControl_RTL.vhd + rm -v -f ./Cursor/hdl/decelerationPositions_RTL.vhd + rm -v -f ./Cursor/hdl/divider_RTL.vhd + rm -v -f ./Cursor/hdl/findDistance_RTL1.vhd + rm -v -f ./Cursor/hdl/positionCounter_RTL.vhd + rm -v -f ./Cursor/hdl/pulseWidthModulator_RTL.vhd + rm -v -f ./Cursor/hds/_amplitudecontrol._epf + rm -v -f ./Cursor/hds/_bridgecontrol._epf + rm -v -f ./Cursor/hds/_control._epf + rm -v -f ./Cursor/hds/_decelerationpositions._epf + rm -v -f ./Cursor/hds/_divider._epf + rm -v -f ./Cursor/hds/_positioncounter._epf + rm -v -f ./Cursor/hds/_pulsewidthmodulator._epf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationpositions_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationPositions_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_findDistance_RTL1.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positioncounter_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positionCounter_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulsewidthmodulator_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulseWidthModulator_RTL.vhd._fpf + rm -v -f -r ./Cursor/hds/amplitude@control + rm -v -f -r ./Cursor/hds/bridge@control + rm -v -f -r ./Cursor/hds/control + rm -v -f -r ./Cursor/hds/deceleration@positions + rm -v -f -r ./Cursor/hds/divider + rm -v -f -r ./Cursor/hds/position@counter + rm -v -f -r ./Cursor/hds/pulse@width@modulator + rm -v -f -r ./Cursor/hds/rising@detector + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-cursor.vhd + +elif [ "$project" == "did-chrono" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-chrono" + rm -v -f ./Chronometer/hdl/coilControl_RTL.vhd + rm -v -f ./Chronometer/hdl/divider1Hz_RTL.vhd + rm -v -f ./Chronometer/hdl/tickLengthCounter_RTL.vhd + rm -v -f ./Chronometer/hdl/lcdDisplay_masterVersion.vhd + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_control._epf + rm -v -f ./Chronometer/hds/_divider1hz._epf + rm -v -f ./Chronometer/hds/_ticklengthcounter._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilcontrol_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilControl_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1hz_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1Hz_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_ticklengthcounter_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_tickLengthCounter_RTL.vhd._fpf + rm -v -f -r ./Chronometer/hds/coil@control/ + rm -v -f -r ./Chronometer/hds/control/ + rm -v -f -r ./Chronometer/hds/divider1@hz/ + rm -v -f -r ./Chronometer/hds/rising@detector/ + rm -v -f -r ./Chronometer/hds/tick@length@counter/ + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-chrono.vhd + +elif [ "$project" == "did-kart-ebs2" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs2 $dir" + + if [ "$dir" == "01-StepperMotor" ]; then + rm -v -f ./01-StepperMotor/StepperMotor/hdl/angleDifference_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/coilControl_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/stepperCounter_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hds/angle@control/master@version.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_shift@reg.bd + elif [ "$dir" == "02-DcMotor" ]; then + rm -v -f ./02-DcMotor/DcMotor/hdl/dcMotorPwm_RTL.vhd + elif [ "$dir" == "03-Sensors" ]; then + rm -v -f ./03-Sensors/Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./03-Sensors/Sensors/hdl/ultrasoundRanger_RTL.vhd + elif [ "$dir" == "04-Controller" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-kart-ebs3" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs3" + rm -v -f ./DcMotor/hdl/dcMotorPwm_RTL.vhd + rm -v -f ./Kart_test/hdl/txFIFO_tester_test.vhd + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tb/ + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tester/ + rm -v -f ./Kart_test/hds/_txfifo_tb._epf + rm -v -f ./Kart_test/hds/_txfifo_tester._epf + rm -v -f -r ./Kart_test/hds/kart@controller_full_tb/ + rm -v -f ./Kart_test/hds/_kartcontroller_full_tb._epf + rm -v -f ./Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./Sensors/hdl/ultrasoundRanger_RTL.vhd + rm -v -f ./Stepper/hdl/angleDifference_RTL.vhd + rm -v -f ./Stepper/hdl/coilControl_RTL.vhd + rm -v -f ./Stepper/hdl/stepperCounter_RTL.vhd + rm -v -f ./Stepper/hds/angle@control/master@version.bd + rm -v -f ./Stepper/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./Stepper/hds/coil@control/master@version_shift@reg.bd + rm -v -f ./Stepper_test/hdl/stepperMotorRegisters_tester_test.vhd + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tb/ + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tester/ + rm -v -f ./Stepper_test/hds/_steppermotorregisters_tb._epf + rm -v -f ./Simulation/Kart/UVM/uvmCommands.txt + rm -v -f ./Simulation/Kart/kartUVM.do + rm -v -f ./Simulation/Kart/txFIFO.do + rm -v -f ./Simulation/Stepper/stepperMotorRegisters.do + rm -v -f -r ./Simulation/UART/ + rm -v -f -r ./UART_test/ + + rm -v -f ./Board/concat/*.vhd + find ./Board/libero/designer/ ! \( -name "*.prjx" -o -name "*.adb" -o -name "*.ide_des" -o -name "*.pdb" -o -name "*_syn.prj" \) -type f -exec rm -v -f -r {} + + rm -v -f -r ./Documentation/ + rm -v -f -r ./CommandInterpreter/src/ + +elif [ "$project" == "did-synchro" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-synchro" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-synchro.vhd + +elif [ "$project" == "did-inverter" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-inverter" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-inverter.vhd + +elif [ "$project" == "did-display" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-display" + find ./Board/ise/ -name "*.mcs" -type f -exec rm -v -f {} + + rm -v -f -r ./Display/concat/ + find ./Display/hdl/ -name "*.vhg" -type f -exec rm -v -f {} + + rm -v -f ./Display/hdl/test_pattern_calculated_rtl.vhd + rm -v -f ./Display/hdl/vgaDataCreator_rgb.vhd + rm -v -f ./Display/hdl/vgaDataSelector_rtl.vhd + rm -v -f ./Display/hds/display@circuit/master@version.bd + rm -v -f -r ./Display/hds/vga@data@calculated/ + rm -v -f -r ./Display/hds/vga@data@selector/ + + rm -v -f -r ./Display_test/concat/ + + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-display.vhd + +elif [ "$project" == "eln_support" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_radio" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_audioamp" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "cansat" ]; then + echo "Error: Not implemented yet" +fi + +echo "Source taken from $repo_source to $repo_dest" + +#------------------------------------------------------------------------------- +# change from masterVersion to studentVersion and delete all masterVersion +# +if [ "$project" == "synd-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "ete-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "isc-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +else + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a master@version -n student@version -r +fi + +# add/commit/push changes to student repo +git add -A +git commit -a -m "$DATE: Automatic Laboratory Update with ``deployLab.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +echo "Delete tmp directory" +cd .. +pwd +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deployLibs.bash b/zz-solutions/02-SplineInterpolator/Scripts/deployLibs.bash new file mode 100644 index 0000000..3498c2b --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deployLibs.bash @@ -0,0 +1,320 @@ +#!/bin/bash + +#================================================================================ +# deployLibs.bash - updates github repos for individual labos +# indend to push libs from [DiD-libs](https://gitlab.hevs.ch/course/did/did-libs.git) +# Example usage 1: ./Scripts/deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +# Example usage 12: ./Scripts/deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' + +usage='Usage: deployLibs.bash [-p projectName] [-r repourl] [-v] [-h]' +while getopts 'p:r:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Libraries for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_dest=`realpath "./Libs"` +library_source=`realpath "./../../.."` +mkdir -p $library_dest + +# Copy needed libraries per project +echo "Update files in student repo $project" +if [ "$project" == "synd-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "ete-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "isc-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "car-labs" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + library_dest=`realpath "./heirv32_sc/Libs"` + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "car-heirv" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "ele_labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, Memory, Modulation, NanoBlaze" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/Modulation" "$library_dest/" + cp -ar "$library_source/Modulation_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "sem-labs" ]; then + echo " Copy libraries: Common, RS232, AhbLite, Memory, RiscV, NanoBlaze" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RiscV" "$library_dest/" + cp -ar "$library_source/RiscV_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "did-cursor" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "did-chrono" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + #cp -ar "$library_source/RS232" "$library_dest/" + #cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs2" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs3" ]; then + echo " Copy libraries: Common, Gates, I2C, Memory, RS232, IO, Sequential, UVM" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/UVM" "$library_dest/" + cp -ar "$library_source/UVM_test" "$library_dest/" +elif [ "$project" == "did-synchro" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-inverter" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Cordic" "$library_dest/" + cp -ar "$library_source/Cordic_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "eln_support" ]; then + echo "Nothing todo, no Libararies needed" +elif [ "$project" == "did-display" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "eptm_radio" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" +elif [ "$project" == "eptm_audioamp" ]; then + echo " Copy libraries: AD_DA, Common, Filter" + cp -ar "$library_source/AD_DA" "$library_dest/" + cp -ar "$library_source/AD_DA_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Filter" "$library_dest/" + cp -ar "$library_source/Filter_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "cansat" ]; then + echo " Copy libraries: AhbLite, AhbLiteComponents, Common, Commandline, Memory, NanoBlaze, RS232" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Commandline" "$library_dest/" + cp -ar "$library_source/Commandline_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Library Update with ``deployLibs.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deployLibsAll.bash b/zz-solutions/02-SplineInterpolator/Scripts/deployLibsAll.bash new file mode 100644 index 0000000..46c6c3c --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deployLibsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployLibsAll.bash - updates github repos for all labo's at once +# indend to push libs from [eda_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployLibs.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +./deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deploySEmLabs.bash b/zz-solutions/02-SplineInterpolator/Scripts/deploySEmLabs.bash new file mode 100644 index 0000000..b36ba70 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deploySEmLabs.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#================================================================================ +# deployLabsAll.bash - updates github repos for all labo's at once +# indend to push labs from [sem-labs](https://gitlab.hevs.ch/course/SEm/hd-labs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + + +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deployScripts.bash b/zz-solutions/02-SplineInterpolator/Scripts/deployScripts.bash new file mode 100644 index 0000000..a91e55b --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deployScripts.bash @@ -0,0 +1,331 @@ +#!/bin/bash + +#================================================================================ +# deployScripts.bash - updates github repos for individual labos +# indend to push scripts from [DiD-scripts](https://gitlab.hevs.ch/course/did/did-scripts.git) +# Example usage 1: ./Scripts/deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +# Example usage 12: ./Scripts/deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory" + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +destdir='' + +usage='Usage: deployScripts.bash [-p projectName] [-r repourl] [-d destdir] [-v] [-h]' +while getopts 'p:r:d:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) destdir=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Scripts for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_source=`realpath "./../.."` + +# DiD Kart (EBS2 version) has a different project structure +if [ "$project" == "did-kart-ebs2" ]; then + # Copy needed libraries per project + mkdir -p "01-StepperMotor/Scripts" + library_dest=`realpath "./01-StepperMotor/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + + # Copy needed libraries per project + mkdir -p "02-DcMotor/Scripts" + library_dest=`realpath "./02-DcMotor/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "03-Sensors/Scripts" + library_dest=`realpath "./03-Sensors/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "04-Controller/Scripts" + library_dest=`realpath "./04-Controller/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + +# SEm Labs has also a different project structure +elif [ "$project" == "sem-labs" ]; then + # Copy needed libraries per project + mkdir -p "01-WaveformGenerator/Scripts" + library_dest=`realpath "./01-WaveformGenerator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "02-SplineInterpolator/Scripts" + library_dest=`realpath "./02-SplineInterpolator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "03-DigitalToAnalogConverter/Scripts" + library_dest=`realpath "./03-DigitalToAnalogConverter/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "04-Lissajous/Scripts" + library_dest=`realpath "./04-Lissajous/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "05-Morse/Scripts" + library_dest=`realpath "./05-Morse/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "06-07-08-09-SystemOnChip/Scripts" + library_dest=`realpath "./06-07-08-09-SystemOnChip/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "10-PipelinedOperators/Scripts" + library_dest=`realpath "./10-PipelinedOperators/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + +else + + if [ -n "$destdir" ]; then + mkdir -p "$destdir/Scripts" + library_dest=`realpath "$destdir/Scripts"` + else + mkdir -p "Scripts" + library_dest=`realpath "./Scripts"` + fi + + # Copy needed libraries per project + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/update_diamond.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + cp -arf "$library_source/start_diamond.pl" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Scripts Update with ``deployScripts.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +#s +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/deployScriptsAll.bash b/zz-solutions/02-SplineInterpolator/Scripts/deployScriptsAll.bash new file mode 100644 index 0000000..bb9e937 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/deployScriptsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployScriptsAll.bash - updates github Scripts folder for all labo's at once +# indend to push scripts from [eda_scripts](https://gitlab.hevs.ch/course/ElN/eda_scripts.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployScripts.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +./deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/generateSSHKey.bash b/zz-solutions/02-SplineInterpolator/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bash b/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bash new file mode 100644 index 0000000..4b54b46 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bat b/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..87ed140 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/hdlDesigner.bat @@ -0,0 +1,278 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... 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z5slpcST}!$8~P7WhC{jTkZBebrDfGX>qt%S4M-;Nv$%o<= zszHu|jpJD5?qJimvJMdQpFucx+aITouUdP_+smI6qL_!#ugDh zN}&D!wbIJZ=~NM2OaCmL(JE0eo`y7Ps(3hK2h=w5YoGVQc9Ny|U|vqAtCg!0C$0W9 z0z)4AdXeNv_SWR7kuBoE1}-HG1G6qnWAer+f!zL;&369C<|K!+^zFa4BoPtmkV3iF zQ(BqSO)6r3wSmd*%x=@4aJB2a#rzbE@&+iQ{R|4!LT0YNwbSoAM{oxJ9xPNZKtbPp z%w?(0Bx7=65BoY!Rwt0`vVXq&VZlqwuh-SpTg}?pYV-GSg-yDasXuWD0a)kuw zYiJcYPers6>b%SE`M +# Parameter : start_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# V0.2 : ama 02.2023 -- Adapted for Diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Diamond +# + +if ($verbose == 1) { + print "$separator\n\n"; + print "Launching Diamond from $designerExe\n"; + print $indent, "* Project file spec: $diamondFileSpec\n\n"; + print "$separator\n\n"; +} + +system("$designerExe $diamondFileSpec"); diff --git a/zz-solutions/02-SplineInterpolator/Scripts/start_libero.pl b/zz-solutions/02-SplineInterpolator/Scripts/start_libero.pl new file mode 100644 index 0000000..3e11301 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/start_libero.pl @@ -0,0 +1,37 @@ +#!/usr/bin/perl +# filename: start_libero.pl +# created by: Corthay Francois & Zahno Silvan +# +#------------------------------------------------------------------------------- +# +# Description: +# Starts Libero in the correct timezone for the Synplify License +# Help Parameter : +# Parameter : start_libero.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Libero +# + +if ($verbose == 1) { + print "\n"; + print "launching $designerExe\n"; + print $indent, "project file spec: $liberoFileSpec\n"; + print "$separator\n"; +} + +system("$designerExe $liberoFileSpec"); \ No newline at end of file diff --git a/zz-solutions/02-SplineInterpolator/Scripts/trimLibs.pl b/zz-solutions/02-SplineInterpolator/Scripts/trimLibs.pl new file mode 100644 index 0000000..efbff23 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/trimLibs.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ------------------------------------------------------------------------------ +# Changelog: +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/zz-solutions/02-SplineInterpolator/Scripts/update_diamond.pl b/zz-solutions/02-SplineInterpolator/Scripts/update_diamond.pl new file mode 100644 index 0000000..92e9076 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Scripts/update_diamond.pl @@ -0,0 +1,129 @@ +#!/usr/bin/perl +# filename: update_diamond.pl +# created by: Corthay Francois & Zahno Silvan & Amand Axel +# +#------------------------------------------------------------------------------- +# +# Description: +# Updates the file references in the .ldf Lattice project file +# and launches the Diamond project manager +# Help Parameter : +# Parameter : update_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# V0.3 : ama 02.2023 -- Adapted for diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$lpfFileSpec = $ARGV[2]; + +use File::Basename; +$diamond_dir = dirname(dirname($vhdlFileSpec)) . '/diamond/'; # get up concat and into diamond +$projectTitle = basename($diamondFileSpec, ".ldf"); + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * diamondFileSpec: $diamondFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * lpfFileSpec: $lpfFileSpec\n"; + print " * Project title: $projectTitle\n" +} + + +#------------------------------------------------------------------------------- +# Project variables +# + +$diamondWorkFileSpec = $diamondFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{DIAMOND_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n\n"; + print "Updating file specifications in $diamondFileSpec\n"; + print $indent, "temporary file spec: $diamondWorkFileSpec\n"; +} +my $line; +if ( !open(DiamondFile, $diamondFileSpec) ){ + print("\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"); + die "\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"; +} + +open(workFile, ">$diamondWorkFileSpec"); +while (chop($line = )) { + + # replace title + if ($line =~ m/ +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +# Parameter : update_libero.pl <^PDC File Spec> +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$pdcFileSpec = $ARGV[2]; + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * liberoFileSpec: $liberoFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * pdcFileSpec: $pdcFileSpec\n"; +} + + + +#------------------------------------------------------------------------------- +# Project variables +# +$liberoWorkFileSpec = $liberoFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{LIBERO_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $liberoFileSpec\n"; + print $indent, "temporary file spec: $liberoWorkFileSpec\n"; +} +my $line; + +open(LiberoFile, $liberoFileSpec) || die "couldn't open $HDLFileSpec!"; +open(workFile, ">$liberoWorkFileSpec"); +while (chop($line = )) { + # replace source path + if ($line =~ m/DEFAULT_IMPORT_LOC/i) { + $line =~ s/".*"/"$sourceDir"/; + } + # replace project path + if ($line =~ m/ProjectLocation/i) { + $line =~ s/".*"/"$projectDir"/; + } + # replace VHDL file spec + if ($line =~ m/VALUE\s".*,hdl"/i) { + $line =~ s/".*"/"$vhdlFileSpec,hdl"/; + } + # replace PDC file spec + if ($line =~ m/VALUE\s".*\.pdc,pdc"/i) { + $line =~ s/".*"/"$pdcFileSpec,pdc"/; + } + + print workFile ("$line\n"); +} + +close(workFile); +close(LiberoFile); + + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($liberoFileSpec); +rename($liberoWorkFileSpec, $liberoFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#------------------------------------------------------------------------------- +# Launch Libero +# + +#if ($verbose == 1) { +# print "\n"; +# print "launching $designerExe\n"; +# print $indent, "project file spec: $liberoFileSpec\n"; +# print "$separator\n"; +#} + +#system("$designerExe $liberoFileSpec"); diff --git a/zz-solutions/02-SplineInterpolator/Simulation/coefficients_sinus.pdf b/zz-solutions/02-SplineInterpolator/Simulation/coefficients_sinus.pdf new file mode 100644 index 0000000000000000000000000000000000000000..6e26f5d2176009db1b04e1ab747f296ff42ed173 GIT binary patch literal 20972 zcmeIacUV(P*FGFVkrI$5T?kD;N)k#4Nbk~{N|P2sk=~2+j)o>xL8>4M2r3E+Ql$tA zg3_CG5D}2xza2d1c-s4WpXxA<&P4BVlS# zQz#OF1V#|oWn{=PE;axca_GPOkdyj(U~F-c5J+-T_-{YJ)YBH!<&Qpbaq)ljp~OV~ z-iLsT{9`TxfsptIo!CF=L`32Lpc4a(`})gZ&;-|1GL=#h7lSJaiwG+#D#{~NkYb7mq=X_uLP1y*g+wZfiONVR ziz%ZNR8UA|aU}(15m6Bd1#tyMWo0qAiio_3h?uer&e5cvUREAnKRpU3C*|f=)=?oR z{kz-ANre$V0}B^d7#BM)d#E@HrsCk_h4Fx?I9YjNlrU&l8w~6+R00JA8%h{v02M*W z$as2rV62>hm>IFQwETjxv>a&$5%_39NbXRcqw|g zx+%E&nZkh{F$pmtVPPmrRQNhD*8}6?^&3}3R~Ikfou?_{ln)dkjAIAIg%a-NR1GNN z)OEm``Pq5uQz!x_N&h${o-hc*XJlo#N+QoLxA{zgzaZM4<0FOu@<%gM$wy z@8MwOq-6-KB#+-<6A^|fy8uhc!Nm@M&qdzF)8UWzf584H2mNDRB2aLVe_5HomZDl* z>a|x1EaH?O7WgGo@eQ98M?(B;-Px*41zZurtql}tV(bseK zsG_aLoO^ioEfzl+rRpYF zpB??jr|+LE-fCf`4GbeY4g{(4;$PLh>cW?l{AqJ_GQ%|^aj@%P`5cAt^@i*7e6{78 zvTP^aDQ8=YUZi)szy6-I4hg9U89&~0_ZM%;&3!TnYcL=EeoOZe{cV=D&>zKT%?dO| z`5}=Uig`f^d3+VYo*N3OUCyMGbAxf#VU$4&U7rR%mfnvvzq~bZO*NA2v1|gv;C|)J z*v@DwiUXF$B!0IZB*&SBdX4YAy0htfONHF3_kE_oigNB6YZl#Ko%kXpy#r#^qbVso zL3!_#GpRP1Ypm+0U)rABo>PejDDf}yyNp6IwC_7@xGn9ceAkTn+AGCBSf_7vo+aMZ zM%_2oDvX0pHuWQAi%PR2S$nyiwFKQkoyXX2Cz3Lal#^u})R+|U%sE-dxpwCfK${`+ zKqsBW+uCQZSSBmUV53T~@ww-*mB(utKW+HE>T9Yq%V*lb-fP)cb z8$MUJ$Iokor<(r|B)fMdBM+^spLq5o=6wA2_Mv0l(MJj|kv3<3@8fuLNy*gjmT}aN zDI$mwM3O`d(No|)<_*OZ7Dnr)cU;xwKI~i)&f(*N-@-UMfjE-9ovDim5zg%_!}xNaL68b1uEUSUE&%hHva#sqpT~ z8F?>a@Csh!lpU=jYAD(Kp;18PsCMl~t5*3e?uT@h*4`kcXwc&zBFhrvUZ!sE*@3w9 zoaN#aU4uIYZt+6fkNA3Tu*X6a^UxrxJ;w0>%RrykMePmFtpsTl=MJRv_)8uxfU8XB znxC641$;5y>f3s>W*J$V`vP*_rz6XB{c>Y6b>N1eNS&Y8+tF+CSHcqHFH1|01zSvT zn2{7~GLU6Bx3u7Uycode@gXfeoj=yL*&DReU)T>{y|iJatZYi~f-aWVmslx={qYP-%i7Hd zUd{&XRNVM`9fGY&WgUdYWsfs*P7HYG7bw&3C(q{FUhygCa{K^@uvPR3$W+%tSdah| zHpF-UY*vGTQ7o}^ca{l^Z>O(Ri7?+W5H;3vlsxx#x3#E7=U>RqElEkX3!9OAz zD=*K~ca$@ACO68bOQZ;2q$C)@CvNExU_FcNby@%T!|BqBLJTtI z#>TuZncvnTC>DZecmQeCeO}s*pIBibor=oRR?tG8@hbU%$N%|9uL31wv|Kx=`G;dh zq9;kk;p;g?jT(nm0!)^i=|JL>yqp}ek1m5}rEXRSj~zJeZz%>LO}%cLa5qa`${kwo zll)TV7B+ANBTDhkC}SoYR<8KkO=ac_7VheeZ_hHOEX)*R(=lyxzAs7yXwB;Ln9U>! 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a/zz-solutions/02-SplineInterpolator/Simulation/sineGen.do b/zz-solutions/02-SplineInterpolator/Simulation/sineGen.do new file mode 100644 index 0000000..df337bb --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Simulation/sineGen.do @@ -0,0 +1,36 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /sinegen_tb/reset +add wave -noupdate /sinegen_tb/clock +add wave -noupdate -format Analog-Step -height 30 -max 1300.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/phase +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/triangle +add wave -noupdate -divider sinewave +add wave -noupdate -format Analog-Step -height 80 -max 43200.0 -min -32800.0 -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/sineSamples +add wave -noupdate /sinegen_tb/I_DUT/newPolynom +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/a +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/b +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/c +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/d +add wave -noupdate -format Analog-Step -height 80 -max 76000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 250 +configure wave -valuecolwidth 52 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {52589 ns} +run 50 us diff --git a/zz-solutions/02-SplineInterpolator/Simulation/waveformGen.do b/zz-solutions/02-SplineInterpolator/Simulation/waveformGen.do new file mode 100644 index 0000000..ce4b33d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/Simulation/waveformGen.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /waveformgen_tb/reset +add wave -noupdate /waveformgen_tb/clock +add wave -noupdate /waveformgen_tb/en +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/triangle +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/polygon +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 272 +configure wave -valuecolwidth 89 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {525 us} +run 500 us diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_masterVersion.vhd new file mode 100644 index 0000000..2bc35ac --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_masterVersion.vhd @@ -0,0 +1,56 @@ +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd new file mode 100644 index 0000000..775bf7a --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS +BEGIN + sampleOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_masterVersion.vhd new file mode 100644 index 0000000..53cd473 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_masterVersion.vhd @@ -0,0 +1,28 @@ +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd new file mode 100644 index 0000000..f213fce --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF interpolatorCoefficients IS +BEGIN + a <= (others => '0'); + b <= (others => '0'); + c <= (others => '0'); + d <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_masterVersion.vhd new file mode 100644 index 0000000..cb4d6b8 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_masterVersion.vhd @@ -0,0 +1,40 @@ +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd new file mode 100644 index 0000000..428b0ab --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF interpolatorShiftRegister IS +BEGIN + sample1 <= (others => '0'); + sample2 <= (others => '0'); + sample3 <= (others => '0'); + sample4 <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_masterVersion.vhd new file mode 100644 index 0000000..8c10d84 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_masterVersion.vhd @@ -0,0 +1,27 @@ +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd new file mode 100644 index 0000000..9dd7350 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF interpolatorTrigger IS +BEGIN + triggerOut <= '0'; +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg new file mode 100644 index 0000000..b9fb637 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg @@ -0,0 +1,34 @@ +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg new file mode 100644 index 0000000..ce5e957 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg @@ -0,0 +1,33 @@ +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg new file mode 100644 index 0000000..e4bedbe --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg @@ -0,0 +1,31 @@ +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg new file mode 100644 index 0000000..b2c73f5 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg @@ -0,0 +1,27 @@ +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_masterVersion.vhd new file mode 100644 index 0000000..76ace80 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_masterVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd new file mode 100644 index 0000000..360c161 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF offsetToUnsigned IS +BEGIN + unsignedOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg new file mode 100644 index 0000000..9ddaacc --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg @@ -0,0 +1,25 @@ +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg new file mode 100644 index 0000000..0915fa0 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg @@ -0,0 +1,26 @@ +-- VHDL Entity SplineInterpolator.resizer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:36 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY resizer IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END resizer ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_masterVersion.vhd new file mode 100644 index 0000000..de8388e --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_masterVersion.vhd @@ -0,0 +1,33 @@ +ARCHITECTURE masterVersion OF resizer IS + +BEGIN + + outGtIn: if resizeOut'length > resizeIn'length generate + begin + resizeOut <= shift_left( + resize( + resizeIn, + resizeOut'length + ), + resizeOut'length-resizeIn'length + ); + end generate outGtIn; + + outEqIn: if resizeOut'length = resizeIn'length generate + begin + resizeOut <= resizeIn; + end generate outEqIn; + + outLtIn: if resizeOut'length < resizeIn'length generate + begin + resizeOut <= resize( + shift_right( + resizeIn, + resizeIn'length-resizeOut'length + ), + resizeOut'length + ); + end generate outLtIn; + +END ARCHITECTURE masterVersion; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd new file mode 100644 index 0000000..3d675a6 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF resizer IS +BEGIN + resizeOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_masterVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_masterVersion.vhd new file mode 100644 index 0000000..9285888 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_masterVersion.vhd @@ -0,0 +1,57 @@ +ARCHITECTURE masterVersion OF sineTable IS + + signal changeSign : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + + signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine + +begin + + changeSign <= phase(phase'high); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1) + begin + if (flipPhase xor shiftPhase) = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if (flipPhase xor shiftPhase) = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine) + begin + if (changeSign xor (flipPhase and shiftPhase)) = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSign; + +END ARCHITECTURE masterVersion; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd new file mode 100644 index 0000000..3d6518d --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd @@ -0,0 +1,27 @@ +ARCHITECTURE studentVersion OF sineTable IS + + signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0); + signal quarterSine : signed(sine'range); + +BEGIN + + phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + quarterTable: process(phaseTableAddress) + begin + case to_integer(phaseTableAddress) is + when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length); + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + sine <= (others => '0'); + +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg new file mode 100644 index 0000000..5a4c177 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg @@ -0,0 +1,31 @@ +-- VHDL Entity SplineInterpolator.sineGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:40 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineGen IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg new file mode 100644 index 0000000..035490a --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg @@ -0,0 +1,307 @@ +-- +-- VHDL Architecture SplineInterpolator.sineGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:42:04 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY SplineInterpolator; +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF sineGen IS + + -- Architecture declarations + constant tableAddressBitNb : positive := 3; + constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb; + constant coeffBitNb : positive := signalBitNb+4; + + -- Internal signal declarations + SIGNAL a : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL b : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL c : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL d : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_ulogic; + SIGNAL newPolynom : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT resizer + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT ( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; + FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; + FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; + FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; + FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; + FOR ALL : resizer USE ENTITY SplineInterpolator.resizer; + FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; + FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; + FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; + FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + logic1 <= '1'; + + -- HDL Embedded Text Block 3 eb3 + logic0 <= '0'; + + + -- Instance port mappings. + I_spline : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom, + d => d, + sampleOut => sineSigned, + c => c, + b => b, + a => a, + en => logic1 + ); + I_coeffs : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4, + a => a, + b => b, + c => c, + d => d, + interpolateLinear => logic0 + ); + I_shReg : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom, + sampleIn => sineSamples, + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom, + clock => clock, + reset => reset, + en => logic1 + ); + I_unsigned : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => sine, + signedIn => sineSigned + ); + I_size : resizer + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb + ) + PORT MAP ( + resizeOut => sawtooth_internal, + resizeIn => phase + ); + I_sin : sineTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sineSamples, + phase => phase + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => logic1 + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle, + sawtooth => sawtooth_internal + ); + + -- Implicit buffered output assignments + sawtooth <= sawtooth_internal; + +END struct; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg new file mode 100644 index 0000000..d3abaef --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg @@ -0,0 +1,27 @@ +-- VHDL Entity SplineInterpolator.sineTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:46 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineTable ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator/hds/.cache.dat b/zz-solutions/02-SplineInterpolator/SplineInterpolator/hds/.cache.dat new file mode 100644 index 0000000000000000000000000000000000000000..d5f763433f8d945d11b5e5fdaf2aa9d44b25ad03 GIT binary patch literal 8272 zcmcgxPj4GV6yG{-<0etu#4XUYQG;6AM6^khQY3D65|dh_O|ebdBE)KKkL{J#yY22e zReGv8a^lVrA;gJ0CoV|v6}Z7S;J}^t#yjiTc=tJuCmG4>+1WSm_x{bBx3ik2%|F_% zELmpFHQd9cx>0X44cgqs{q;{)HNlJ2l5z^=e2w&3@E>*EI77=ucK&Jl@>f<->S^ zh5-DMx`#b%;ZXmM_uz6XitMmv)2y4!_Puz}Cd?Td^mYW)Ynx3!@3NNZfvI9)8~>_+ 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to_unsigned(1, step'length); + +END ARCHITECTURE test; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg new file mode 100644 index 0000000..844b740 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:04 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY sineGen_tb IS +-- Declarations + +END sineGen_tb ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg new file mode 100644 index 0000000..66bab33 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tb_struct.vhg @@ -0,0 +1,108 @@ +-- +-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:41:39 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY SplineInterpolator; +LIBRARY SplineInterpolator_test; + +ARCHITECTURE struct OF sineGen_tb IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 10; + constant clockFrequency: real := 60.0E6; + --constant clockFrequency: real := 66.0E6; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT sineGen + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineGen_tester + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10; + clockFrequency : real := 60.0E6 + ); + PORT ( + sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0); + sine : IN unsigned (signalBitNb-1 DOWNTO 0); + square : IN unsigned (signalBitNb-1 DOWNTO 0); + triangle : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : OUT std_ulogic ; + reset : OUT std_ulogic ; + step : OUT unsigned (phaseBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen; + FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_DUT : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => step, + sawtooth => sawtooth, + sine => sine, + square => square, + triangle => triangle + ); + I_tb : sineGen_tester + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + clockFrequency => clockFrequency + ) + PORT MAP ( + sawtooth => sawtooth, + sine => sine, + square => square, + triangle => triangle, + clock => clock, + reset => reset, + step => step + ); + +END struct; diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg new file mode 100644 index 0000000..dfc1ae3 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hdl/sinegen_tester_entity.vhg @@ -0,0 +1,32 @@ +-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:41:39 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +ENTITY sineGen_tester IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10; + clockFrequency : real := 60.0E6 + ); + PORT( + sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0); + sine : IN unsigned (signalBitNb-1 DOWNTO 0); + square : IN unsigned (signalBitNb-1 DOWNTO 0); + triangle : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : OUT std_ulogic; + reset : OUT std_ulogic; + step : OUT unsigned (phaseBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen_tester ; + diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat new file mode 100644 index 0000000000000000000000000000000000000000..5726ca0ac59c307e2f453c6bb746df61dda84999 GIT binary patch literal 1571 zcmcgs%}(1u5H@K;Dnc8e5<)#i>IJGckfqpQo?Dd}CvrVxhL6j^y#|&g^{ir_nTRVaMoJea{K)a9nk5_f%>`^NqFoX01_O zZjL;^UtM3pbf}rjn0^5^jhVBQpOokbzLnYNW!Et7=Xk znzFnQKQ-+KEZ;QS2V1+su=G|(-(xKp5u7qBe1Zf@ukKGQ5t~FCpE*On7CF!+XyysY zrS9=w^PtVwU_`0UKZ1F8pA_XT!&MLU_-4CYxCF|+BENHSV%C1o>}=~>Ca}t2M1P0L zsl{~^GEklx*S?<);HNAv-+v@`A4smW%zd+?_e?_^?if!74`bYXV|>7eINhSW;Pg|$&f6_mJReaj|603r-rxy<-}Nu zyAN$TusHmOXc#8L5Z$yTjIZ1YMDzCHI)eSHq<)YmgQkn(FEESt(VhCSrIyo*2Og&` t$WxACF}oS#K&FA2A@-Fy=ZQH@ncQ>Pt(t9DykPSpdu;a8sI}z1b_)(V`~Cm` literal 0 HcmV?d00001 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf new file mode 100644 index 0000000..2db81c2 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_entity.xrf @@ -0,0 +1,12 @@ +DESIGN sine@gen_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN sine@gen_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN sine@gen_tb +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN sine@gen_tb +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf new file mode 100644 index 0000000..41cdaa3 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tb_struct.xrf @@ -0,0 +1,153 @@ +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 0,0 16 2 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 1,0 19 0 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 19 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 53,0 25 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 45,0 26 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 933,0 27 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 909,0 28 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 925,0 29 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 996,0 30 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 917,0 31 0 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 32 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 33 +LIBRARY SplineInterpolator +DESIGN sine@gen +VIEW struct +GRAPHIC 1519,0 35 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 14,0 36 1 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 52,0 41 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 88,0 42 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 128,0 43 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 98,0 44 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 103,0 45 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 108,0 46 0 +DESIGN sine@gen +VIEW symbol.sb +GRAPHIC 118,0 47 0 +LIBRARY SplineInterpolator_test +DESIGN sine@gen_tester +VIEW test +GRAPHIC 421,0 50 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 14,0 51 1 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 935,0 57 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 911,0 58 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 927,0 59 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 919,0 60 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 55,0 61 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 47,0 62 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 998,0 63 0 +LIBRARY SplineInterpolator_test +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 66 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 1519,0 69 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 421,0 70 0 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 73 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 75 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 1519,0 77 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 1526,0 78 1 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 55,0 83 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 47,0 84 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 998,0 85 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 935,0 86 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 911,0 87 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 927,0 88 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 919,0 89 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 421,0 91 0 +DESIGN sine@gen_tb +VIEW struct.bd +GRAPHIC 428,0 92 1 +DESIGN sine@gen_tb +VIEW struct.bd +NO_GRAPHIC 107 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf new file mode 100644 index 0000000..8ae96cb --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/.xrf/sinegen_tester_entity.xrf @@ -0,0 +1,36 @@ +DESIGN sine@gen_tester +VIEW interface +NO_GRAPHIC 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 50,0 8 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 13,0 13 1 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 409,0 19 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 414,0 20 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 419,0 21 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 429,0 22 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 399,0 23 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 404,0 24 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 424,0 25 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 1,0 28 0 +DESIGN sine@gen_tester +VIEW interface +GRAPHIC 1,0 29 0 diff --git a/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf new file mode 100644 index 0000000..5d5516c --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sine@gen_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git 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+) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *95 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,0,49000,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,1000,45400,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,7600,45000,8600" +st "User:" +blo "42000,8400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "42000,0,49600,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,8600,44000,8600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 447,0 +activeModelName "Symbol:GEN" +) diff --git a/zz-solutions/02-SplineInterpolator/splineInterpolator.bash b/zz-solutions/02-SplineInterpolator/splineInterpolator.bash new file mode 100644 index 0000000..933ab09 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/splineInterpolator.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/zz-solutions/02-SplineInterpolator/splineInterpolator.bat b/zz-solutions/02-SplineInterpolator/splineInterpolator.bat new file mode 100644 index 0000000..bc1b2a4 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/splineInterpolator.bat @@ -0,0 +1,83 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +set HDS_HOME=C:\MentorGraphics\HDS_2019.2 +set MODELSIM_HOME=C:\modeltech64_2021.3\win64 +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +set LM_LICENSE_FILE=27001@mentorlm.hevs.ch + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/02-SplineInterpolator/splineInterpolator.bat.bak b/zz-solutions/02-SplineInterpolator/splineInterpolator.bat.bak new file mode 100644 index 0000000..efe9b97 --- /dev/null +++ b/zz-solutions/02-SplineInterpolator/splineInterpolator.bat.bak @@ -0,0 +1,79 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_masterVersion.vhd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_masterVersion.vhd new file mode 100644 index 0000000..3265bf1 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_masterVersion.vhd @@ -0,0 +1,29 @@ +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd new file mode 100644 index 0000000..c03bc9a --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF DAC IS +BEGIN + serialOut <= '0'; +END ARCHITECTURE studentVersion; diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_masterVersion.vhd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_masterVersion.vhd new file mode 100644 index 0000000..c012da9 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_masterVersion.vhd @@ -0,0 +1,59 @@ +ARCHITECTURE order2_masterVersion OF DAC IS + + constant attenuationShift: positive := 3; + constant acc1BitNb: positive := parallelIn'length+5; + constant acc2BitNb: positive := parallelIn'length+5; + signal parallelIn1, parallelIn2: signed(parallelIn'high downto 0); + signal acc1: signed(acc1BitNb-1 downto 0); + signal acc2: signed(acc2BitNb-1 downto 0); + constant c1: signed(acc1'range) + := shift_left(to_signed(1, acc1'length), parallelIn'length-1); + constant c2: signed(acc2'range) + := resize(shift_left(c1, 4), acc2'length); + signal quantized: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- offset input to signed values + + parallelIn1(parallelIn1'high) <= not parallelIn(parallelIn'high); + parallelIn1(parallelIn1'high-1 downto 0) <= + signed(parallelIn(parallelIn'high-1 downto 0)); + -- attenuate signal + parallelIn2 <= parallelIn1 - shift_right(parallelIn1, attenuationShift); + + ------------------------------------------------------------------------------ + -- SD integrators + integrate1: process(reset, clock) + begin + if reset = '1' then + acc1 <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '1' then + acc1 <= acc1 + resize(parallelIn2, acc1'length) - c1; + else + acc1 <= acc1 + resize(parallelIn2, acc1'length) + c1; + end if; + end if; + end process integrate1; + + integrate2: process(reset, clock) + begin + if reset = '1' then + acc2 <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '1' then + acc2 <= acc2 + resize(acc1, acc2'length) - c2; + else + acc2 <= acc2 + resize(acc1, acc2'length) + c2; + end if; + end if; + end process integrate2; + + ------------------------------------------------------------------------------ + -- test last integrator output + quantized <= '1' when acc2 >= 0 else '0'; + serialOut <= quantized; + +END ARCHITECTURE order2_masterVersion; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd new file mode 100644 index 0000000..fb41871 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE order2_studentVersion OF DAC IS +BEGIN + serialOut <= '0'; +END ARCHITECTURE order2_studentVersion; diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/dac_entity.vhg b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/dac_entity.vhg new file mode 100644 index 0000000..5266b9c --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/dac_entity.vhg @@ -0,0 +1,27 @@ +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_masterVersion.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_masterVersion.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_masterVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_masterVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git 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"0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *82 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,9000,5400,10000" +st "Declarations" +blo "0,9800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,10000,2700,11000" +st "Ports:" +blo "0,10800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,14600,2500,15500" +st "User:" +blo "0,15300" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,9000,5800,10000" +st "Internal User:" +blo "0,9800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,15500,2000,15500" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 172,0 +activeModelName "Symbol" +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/_dac._epf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/_dac._epf new file mode 100644 index 0000000..0c52b64 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/_dac._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom DAC_order1_masterVersion.vhd diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd new file mode 100644 index 0000000..843d64b --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd @@ -0,0 +1,38 @@ +library ieee; + use ieee.math_real.all; + +ARCHITECTURE test OF DAC_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + + signal sineFrequency: real := 20.0E3; + signal tReal: real := 0.0; + signal outAmplitude: real := 1.0; + signal outReal: real := 0.0; + signal outUnsigned: unsigned(parallelIn'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- time signals + process(sClock) + begin + if rising_edge(sClock) then + tReal <= tReal + 1.0/clockFrequency; + end if; + end process; + + outReal <= outAmplitude * ( sin(2.0*math_pi*sineFrequency*tReal) + 1.0) / 2.0; + + outUnsigned <= to_unsigned(integer(outReal * real(2**(outUnsigned'length)-1)), outUnsigned'length); + parallelIn <= outUnsigned; +-- parallelIn <= shift_left(to_unsigned(1, parallelIn'length), parallelIn'length-1); +-- parallelIn <= shift_left(to_unsigned(3, parallelIn'length), parallelIn'length-2); + +END ARCHITECTURE test; diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_entity.vhg b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_entity.vhg new file mode 100644 index 0000000..ad0a660 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity DigitalToAnalogConverter_test.DAC_tb.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:05:57 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY DAC_tb IS +-- Declarations + +END DAC_tb ; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_struct.vhg b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_struct.vhg new file mode 100644 index 0000000..0d2aa5a --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tb_struct.vhg @@ -0,0 +1,122 @@ +-- +-- VHDL Architecture DigitalToAnalogConverter_test.DAC_tb.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:43:18 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY DigitalToAnalogConverter; +LIBRARY DigitalToAnalogConverter_test; +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF DAC_tb IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant lowpassShiftBitNb: positive := 8; + constant clockFrequency: real := 60.0E6; + --constant clockFrequency: real := 66.0E6; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL lowpassIn : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL lowpassOut : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL parallelIn : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL reset : std_ulogic; + SIGNAL serialOut : std_ulogic; + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT DAC_tester + GENERIC ( + signalBitNb : positive := 16; + clockFrequency : real := 60.0E6 + ); + PORT ( + lowpassOut : IN unsigned (signalBitNb-1 DOWNTO 0); + serialOut : IN std_ulogic ; + clock : OUT std_ulogic ; + parallelIn : OUT unsigned (signalBitNb-1 DOWNTO 0); + reset : OUT std_ulogic + ); + END COMPONENT; + COMPONENT lowpass + GENERIC ( + signalBitNb : positive := 16; + shiftBitNb : positive := 12 + ); + PORT ( + lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; + FOR ALL : DAC_tester USE ENTITY DigitalToAnalogConverter_test.DAC_tester; + FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + LowpassIn <= (others => serialOut); + + + -- Instance port mappings. + I_DUT : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => serialOut, + parallelIn => parallelIn, + clock => clock, + reset => reset + ); + I_tester : DAC_tester + GENERIC MAP ( + signalBitNb => signalBitNb, + clockFrequency => clockFrequency + ) + PORT MAP ( + lowpassOut => lowpassOut, + serialOut => serialOut, + clock => clock, + parallelIn => parallelIn, + reset => reset + ); + I_filt : lowpass + GENERIC MAP ( + signalBitNb => signalBitNb, + shiftBitNb => lowpassShiftBitNb + ) + PORT MAP ( + lowpassOut => lowpassOut, + clock => clock, + reset => reset, + lowpassIn => lowpassIn + ); + +END struct; diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tester_entity.vhg b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tester_entity.vhg new file mode 100644 index 0000000..9a28e7d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/dac_tester_entity.vhg @@ -0,0 +1,29 @@ +-- VHDL Entity DigitalToAnalogConverter_test.DAC_tester.interface +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:43:18 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +ENTITY DAC_tester IS + GENERIC( + signalBitNb : positive := 16; + clockFrequency : real := 60.0E6 + ); + PORT( + lowpassOut : IN unsigned (signalBitNb-1 DOWNTO 0); + serialOut : IN std_ulogic; + clock : OUT std_ulogic; + parallelIn : OUT unsigned (signalBitNb-1 DOWNTO 0); + reset : OUT std_ulogic + ); + +-- Declarations + +END DAC_tester ; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_entity.vhg._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_struct.vhg._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tester_entity.vhg._fpf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_entity.xrf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_entity.xrf new file mode 100644 index 0000000..2c6c191 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_entity.xrf @@ -0,0 +1,12 @@ +DESIGN @d@a@c_tb +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN @d@a@c_tb +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN @d@a@c_tb +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN @d@a@c_tb +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_struct.xrf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_struct.xrf new file mode 100644 index 0000000..6424012 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tb_struct.xrf @@ -0,0 +1,172 @@ +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 0,0 17 2 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1,0 20 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 20 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 53,0 26 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1091,0 27 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1081,0 28 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 362,0 29 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 45,0 30 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 364,0 31 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 32 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 33 +LIBRARY DigitalToAnalogConverter +DESIGN @d@a@c +VIEW master@version +GRAPHIC 1298,0 35 0 +DESIGN @d@a@c +VIEW symbol.sb +GRAPHIC 14,0 36 1 +DESIGN @d@a@c +VIEW symbol.sb +GRAPHIC 67,0 40 0 +DESIGN @d@a@c +VIEW symbol.sb +GRAPHIC 57,0 41 0 +DESIGN @d@a@c +VIEW symbol.sb +GRAPHIC 52,0 42 0 +DESIGN @d@a@c +VIEW symbol.sb +GRAPHIC 76,0 43 0 +LIBRARY DigitalToAnalogConverter_test +DESIGN @d@a@c_tester +VIEW test +GRAPHIC 421,0 46 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 14,0 47 1 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1083,0 52 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 366,0 53 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 55,0 54 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 63,0 55 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 47,0 56 0 +LIBRARY WaveformGenerator +DESIGN lowpass +VIEW master@version +GRAPHIC 1056,0 59 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 14,0 60 1 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 57,0 65 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 52,0 66 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 76,0 67 0 +DESIGN lowpass +VIEW symbol.sb +GRAPHIC 83,0 68 0 +LIBRARY DigitalToAnalogConverter_test +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 71 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1298,0 74 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 421,0 75 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1056,0 76 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 79 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1099,0 82 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 84 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 85 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1298,0 87 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1305,0 88 1 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 366,0 92 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 63,0 93 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 55,0 94 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 47,0 95 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 421,0 97 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 428,0 98 1 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1056,0 109 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1063,0 110 1 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1083,0 115 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1073,0 116 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1065,0 117 0 +DESIGN @d@a@c_tb +VIEW struct.bd +GRAPHIC 1093,0 118 0 +DESIGN @d@a@c_tb +VIEW struct.bd +NO_GRAPHIC 121 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tester_entity.xrf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tester_entity.xrf new file mode 100644 index 0000000..706d84d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.xrf/dac_tester_entity.xrf @@ -0,0 +1,30 @@ +DESIGN @d@a@c_tester +VIEW interface +NO_GRAPHIC 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 50,0 8 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 13,0 13 1 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 360,0 18 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 375,0 19 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 355,0 20 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 365,0 21 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 370,0 22 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 1,0 25 0 +DESIGN @d@a@c_tester +VIEW interface +GRAPHIC 1,0 26 0 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/@d@a@c_tb/struct.bd b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/@d@a@c_tb/struct.bd new file mode 100644 index 0000000..0e8b820 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/@d@a@c_tb/struct.bd @@ -0,0 +1,3271 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "DigitalToAnalogConverter_test" +duName "DAC_tester" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 421,0 +) +(Instance +name "I_filt" +duLibraryName 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+va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Verdana,8,0" +) +xt "28200,50000,31600,51000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*82 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,49000,49000,50000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Verdana,8,0" +) +xt "32200,49000,46300,50000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "28000,46000,69000,51000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color 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+thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *87 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,0,49000,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,1000,45400,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,6000,45000,7000" +st "User:" +blo "42000,6800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "42000,0,49600,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,7000,44000,7000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 389,0 +activeModelName "Symbol:GEN" +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf new file mode 100644 index 0000000..066bc61 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom @d@a@c_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf new file mode 100644 index 0000000..2a4c41f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom DAC_tester_test.vhd diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds.hdp b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds.hdp new file mode 100644 index 0000000..8d4c2df --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds.hdp @@ -0,0 +1,31 @@ +[Concat] +[ModelSim] +DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter +DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hdl +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hds +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..c09cedf --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6092 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/04-Lissajous/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/03-DigitalToAnalogConverter/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont 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+genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f0a0260 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/DAC.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "qws" +Description "Quartus Workspace" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "args" +Description "Quartus Arguments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rpt" +Description "Quartus Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "summary" +Description "Quartus Summary File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "eqn" +Description "Quartus Equation File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pin" +Description "Quartus Pin Information File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "vqm" +Description "Quartus Verilog Mapping File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\vqm.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdo" +Description "Standard Delay File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "csv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ppt" +Description "Microsoft PowerPoint Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\powerpoint.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "vsd" +Description "Microsoft Visio Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\visio.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "htm" +Description "HTM File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "html" +Description "HTML File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psl" +Description "Property Specification Language File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\psl.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xlsm" +Description "Excel macro-enabled spreadsheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "rcf" +Description "RA control file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\RaCtrlFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "js" +Description "Javascript" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jsFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "xml" +Description "xml file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Sublime Text" +second "sublime_text.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l) -ro" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 4 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "$TEMP" +projectPaths [ +"hds.hdp" +"D:\\Labs\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\Users\\oliver.gubler\\eda\\VHDL\\labs\\ELN_cursor\\Prefs\\hds.hdp" +"R:\\SYND\\Ele_2131\\ELN\\Labs\\Cursor\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\work\\git\\Education\\Projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\eln_labs.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\hds.hdp" +] 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"8000,2000" +compStateBoxDefaultSize "8000,4000" +waitTextVaSet (VaSet +fg "0,0,32768" +font "Verdana,10,1" +) +sBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +sBlockActionsVaSet (VaSet +) +priorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineWidth 1 +) +priorityNameVaSet (VaSet +) +actionBoxShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +lineWidth 1 +) +actionBoxActionsVaSet (VaSet +) +actionBoxMinimumSize "8000,2000" +actionBoxDefaultSize "8000,4000" +compActionBoxShapeVaSet (VaSet +vasetType 1 +fg "32768,32768,32768" +lineWidth 1 +) +compActionBoxNameVaSet (VaSet +font "Verdana,10,1" +) +compActionBoxMinimumSize "8000,2000" +compActionBoxDefaultSize "8000,4000" +decisionBoxShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 1 +) +decisionBoxConditionVaSet (VaSet +) +decisionBoxLabelVaSet (VaSet +fg "32768,0,0" +font "Verdana,9,1" +) +decisionBoxMinimumSize "8000,2000" +startPointShapeVaSet (VaSet +vasetType 1 +fg "49152,0,49152" +lineWidth 1 +) +startPointLabelVaSet (VaSet +fg "65535,65535,65535" +font "Verdana,10,1" +) +startPointMinimumSize "6000,2000" +endPointShapeVaSet (VaSet +vasetType 1 +fg "49152,0,49152" +lineWidth 1 +) +endPointLabelVaSet (VaSet +fg "65535,65535,65535" +font "Verdana,10,1" +) +endPointMinimumSize "6000,2000" +linkShapeVaSet (VaSet +vasetType 1 +fg "0,32896,0" +) +linkNameVaSet (VaSet +font "Verdana,9,1" +) +caseShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 1 +) +caseLabelVaSet (VaSet +font "Verdana,9,1" +) +caseExpressionVaSet (VaSet +) +caseMinimumSize "14000,4000" +caseDefaultSize "28000,4000" +endCaseShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 1 +) +endCaseLabelVaSet (VaSet +font "Verdana,9,1" +) +endCaseMinimumSize "8000,4000" +ifDecodeShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 1 +) +ifDecodeLabelVaSet (VaSet +font "Verdana,9,1" +) +ifDecodeMinimumSize "14000,4000" +ifDecodeDefaultSize "28000,4000" +endIfShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 1 +) +endIfLabelVaSet (VaSet +font "Verdana,9,1" +) +endIfDecodeMinimumSize "8000,4000" +branchPortShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +fillStyle 12 +) +branchPortNameVaSet (VaSet +font "Verdana,9,1" +) +flowShapeVaSet (VaSet +vasetType 3 +) +flowJoinVaSet (VaSet +vasetType 1 +) +flowConnectShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +fillStyle 12 +) +flowConnectSize "1000,1000" +signalStatLabelVaSet (VaSet +font "Verdana,9,1" +) +signalStatValueVaSet (VaSet +font "Courier New,8,0" +) +declLabelVaSet (VaSet +font "Verdana,9,1" +) +declValueVaSet (VaSet +) +stmtLabelVaSet (VaSet +font "Verdana,9,1" +) +stmtValueVaSet (VaSet +) +visibilityPrefs [ +(StringToBool +display "Architecture Declarations" +status 1 +) +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Concurrent Statements" +status 1 +) +(StringToBool +display "Global Actions" +status 1 +) +(StringToBool +display "Module Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +(StringToBool +display "Process Declarations" +status 1 +) +(StringToBool +display "Signal Status" +status 1 +) +(StringToBool +display "State Register Statements" +status 1 +) +] +) +(BdPreferences +version "1.1" +defaultSaveName "struct" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +hdlTextName "eb1" +signalName "sig0" +busName "dbus0" +vhdlSignalType "std_ulogic" +vhdlBusType "unsigned" +vhdlConstraintType 0 +vhdlBounds "(15 DOWNTO 0)" +verilogType "wire" +verilogLeftBound "15" +verilogRightBound "0" +bundleName "bundle0" +instanceName "U_0" +globalConnectorName "G" +showAttributes 0 +syntaxChecked 1 +useSymbolAttributes 1 +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declaration" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +showVhdlSignalName 1 +showVhdlTypeConstraint 1 +showVhdlTypeFields 0 +showVhdlInitValue 0 +showVhdlSignalDeclSameLine 1 +vhdlConstraintFullForm 0 +showVlogSignalName 1 +showVlogTypeConstraint 1 +showVlogTypeFields 0 +showVlogDelay 0 +showVlogSignalDeclSameLine 1 +showVlog2kSignalName 1 +showVlog2kTypeConstraint 1 +showVlog2kTypeFields 0 +showVlog2kDelay 0 +showVlog2kSignalDeclSameLine 1 +showVlog2kValue 0 +showVlog2kSigned 0 +showVhdlPortName 1 +showVhdlPortTypeConstraint 0 +showVhdlPortTypeFields 0 +showVhdlPortInitValue 0 +showVhdlPortDeclSameLine 1 +vhdlPortConstraintFullForm 0 +showVlogPortName 1 +showVlogPortTypeConstraint 0 +showVlogPortTypeFields 0 +showVlogPortDelay 0 +showVlogPortDeclSameLine 1 +showVlog2kPortName 1 +showVlog2kPortTypeConstraint 0 +showVlog2kPortTypeFields 0 +showVlog2kPortDelay 0 +showVlog2kPortDeclSameLine 1 +showVlog2kPortValue 0 +showVlog2kPortSigned 0 +connectorShape 2 +blockVaSet (VaSet +vasetType 1 +fg "39936,56832,65280" +lineColor "0,0,32768" +lineWidth 2 +) +cptVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +blockPortVaSet (VaSet +vasetType 1 +) +blockPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +hdlTextVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +globalConnectorVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +ripperVaSet (VaSet +vasetType 1 +) +portIoVaSet (VaSet +vasetType 1 +fg "0,0,32768" +) +portIoBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +) +danglingDotShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "65535,0,0" +) +signalVaSet (VaSet +vasetType 3 +) +busVaSet (VaSet +vasetType 3 +lineWidth 2 +) +bundleVaSet (VaSet +vasetType 3 +lineColor "32768,0,0" +lineWidth 2 +) +blockFontVaSet (VaSet +font "Verdana,9,1" +) +cptFontVaSet (VaSet +font "Verdana,9,1" +) +signalFontVaSet (VaSet +) +bundleFontVaSet (VaSet +) +cptPortFontVaSet (VaSet +) +hdlTextFontVaSet (VaSet +font "Verdana,9,1" +) +embeddedTextVaSet (VaSet +) +embeddedTextShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +globalConnectorFontVaSet (VaSet +font "Verdana,9,1" +) +genericAssocFontVaSet (VaSet +font "Courier New,8,0" +) +portMapFrameVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +portMapNameVaSet (VaSet +) +genFrameVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 2 +lineWidth 3 +) +blkFrameVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "26368,26368,26368" +lineStyle 1 +lineWidth 3 +) +frameTxtVaSet (VaSet +) +foreignCptVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +order 0 +archDeclarativeBlockLabelText "Declarations" +archDeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archDeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +blockCellsVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,1" +) +componentCellsVaSet (VaSet +vasetType 4 +bg "45055,65535,30000" +font "Tahoma,10,1" +) +modulewareCellsVaSet (VaSet +vasetType 4 +bg "0,65535,65535" +font "Tahoma,10,1" +) +ipCellsVaSet (VaSet +vasetType 4 +bg "45055,65535,30000" +font "Tahoma,10,1" +) +embeddedBlockCellsVaSet (VaSet +vasetType 4 +bg "65535,65535,37120" +font "Tahoma,10,1" +) +expressionRowVaSet (VaSet +vasetType 4 +bg "65280,65280,46080" +font "Tahoma,10,1" +alignment 0 +) +sliceRowsVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,1" +alignment 0 +) +bundleRowsVaSet (VaSet +vasetType 4 +bg "65280,65280,46080" +font "Tahoma,10,1" +alignment 0 +) +propColumnVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,1" +) +groupColumnVaSet (VaSet +vasetType 4 +bg "62965,57054,46003" +font "Tahoma,10,1" +alignment 0 +) +interfaceColumnVaSet (VaSet +vasetType 4 +bg "59904,39936,65280" +font "Tahoma,10,1" +) +frameColumnVaSet (VaSet +vasetType 4 +fg "65535,65535,65535" +bg "0,0,65535" +font "Tahoma,10,1" +alignment 0 +) +propRowVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,1" +alignment 0 +) +groupRowVaSet (VaSet +vasetType 4 +bg "62965,57054,46003" +font "Tahoma,10,1" +alignment 0 +) +netRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +) +(FcPreferences +version "1.1" +defaultSaveName "flow" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +actionBoxShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +actionBoxNameVaSet (VaSet +fg "0,32768,49152" +) +actionBoxActionsVaSet (VaSet +) +compActionBoxShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineWidth 2 +) +compActionBoxNameVaSet (VaSet +font "Verdana,10,1" +) +decisionBoxShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,37120" +lineWidth 2 +) +decisionBoxNameVaSet (VaSet +fg "0,32768,49152" +) +decisionBoxConditionVaSet (VaSet +) +decisionBoxLabelVaSet (VaSet +fg "32768,0,0" +font "Verdana,9,1" +) +waitBoxShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +waitBoxNameVaSet (VaSet +fg "0,32768,49152" +) +waitBoxConditionVaSet (VaSet +) +startPointShapeVaSet (VaSet +vasetType 1 +fg "49152,0,49152" +lineWidth 2 +) +startPointLabelVaSet (VaSet +fg "65535,65535,65535" +font "Verdana,10,1" +) +endPointShapeVaSet (VaSet +vasetType 1 +fg "49152,0,49152" +lineWidth 2 +) +endPointLabelVaSet (VaSet +fg "65535,65535,65535" +font "Verdana,10,1" +) +startLoopShapeVaSet (VaSet +vasetType 1 +fg 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+archDeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archDeclarativeBlockValueVaSet (VaSet +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +processDeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclarativeBlockValueVaSet (VaSet +) +sensitivityListBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +sensitivityListBlockValueVaSet (VaSet +) +visibilityPrefs [ +(StringToBool +display "Architecture Declarations (VHDL)" +status 1 +) +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Concurrent Statements" +status 1 +) +(StringToBool +display "Local Declarations (Verilog)" +status 1 +) +(StringToBool +display "Module Declarations (Verilog)" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +(StringToBool +display "Process Declarations (VHDL)" +status 1 +) +(StringToBool +display "Sensitivity List" +status 1 +) +] +) +(HdmBrowserPreferences +version "1.1" +ViewpointsPresent_V2 1 +Viewpoints_V2 [ +(Viewpoint_v2 +name "Default Viewpoint" +masterDefault 1 +TreeListVPDatas [ +(TreeListVPData +theList "" +columns [ +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Design Units" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Top Marker" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Size" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" +) +(Viewpoint_v2 +name "Version Management" +TreeListVPDatas [ +(TreeListVPData +theList "Design Units" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +(TreeListVPData_Column +name "Version Management Lockers" +displayName "VM Lockers" +width 85 +) +(TreeListVPData_Column +name "Version Management Versions" +displayName "VM Versions" +width 85 +) +(TreeListVPData_Column +name "Version Management Labels" +displayName "VM Labels" +width 85 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +(TreeListVPData_Column +name "Version Management Versions" +displayName "VM Versions" +width 85 +) +(TreeListVPData_Column +name "Version Management Labels" +displayName "VM Labels" +width 85 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +(TreeListVPData_Column +name "Version Management Versions" +displayName "VM Versions" +width 85 +) +(TreeListVPData_Column +name "Version Management Labels" +displayName "VM Labels" +width 85 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Top Marker" +width 22 +alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name 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+(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 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/dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..63ce98f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6842 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name 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"Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f0a0260 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/DAC.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/.gitlab-ci.yml b/zz-solutions/03-DigitalToAnalogConverter/Scripts/.gitlab-ci.yml new file mode 100644 index 0000000..9d1d7af --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/.gitlab-ci.yml @@ -0,0 +1,53 @@ +stages: + - deploy + +image: alpine:latest + +scripts: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployScriptsAll.bash + - deployScripts.bash + - /*.{pl} + - when: manual + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Bash" + - apk add bash + - echo "Install Core Utils" + - apk add coreutils + - echo "Install Git" + - apk add git + - echo "Set Git credentials" + - git config --global user.email "silvan.zahno@hevs.ch" + - git config --global user.name "Silvan Zahno" + - echo "Setting up deploy-eda_scripts environment" + + script: + - bash ./deployScriptsAll.bash + +libs_trigger: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployLibsAll.bash + - deployLibs.bash + - when: manual + variables: + GIT_CHECKOUT: "false" + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Curl" + - apk add curl + + script: + - 'curl -X POST --fail -F token=glptt-0235c37f03e3060733df7d1151555fd0c63d0adb -F ref=master "https://gitlab.hevs.ch/api/v4/projects/762/trigger/pipeline"' diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/LICENSE b/zz-solutions/03-DigitalToAnalogConverter/Scripts/LICENSE new file mode 100644 index 0000000..fdf8bfa --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/LICENSE @@ -0,0 +1,11 @@ +All Rights Reserved + +Copyright (c) 2019 - HES-SO Valais Wallis + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/README.md b/zz-solutions/03-DigitalToAnalogConverter/Scripts/README.md new file mode 100644 index 0000000..618a38f --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/README.md @@ -0,0 +1,238 @@ +

+
+ EDA scripts Logo +
+ Hevs EDA Scripts +
+

+ +

Common Files and Scripts for ELN Laboratories practical sessions.

+ +[![pipeline status](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/pipeline.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) +[![coverage report](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/coverage.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) + +# Table of contents + + +## Description +[(Back to top)](#table-of-contents) + +These scripts can be used as for: +**Git Repos** +* [EDA_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +* [ELN_labs](https://gitlab.hevs.ch/course/ElN/eln_labs.git) +* [SEm_exams](https://gitlab.hevs.ch/course/SEm/exams.git) +* [ELN_chrono](https://gitlab.hevs.ch/course/ElN/eln_chrono.git) +* [ELN_cursor](https://gitlab.hevs.ch/course/ElN/eln_cursor.git) +* [ELN_kart](https://gitlab.hevs.ch/course/ElN/eln_kart.git) +* [ELN_inverter](https://gitlab.hevs.ch/course/ElN/eln_inverter.git) +* [ELN_synchro](https://gitlab.hevs.ch/course/ElN/eln_synchro.git) +* [SEm_labs](https://gitlab.hevs.ch/course/SEm/sem_labs.git) +* [ELN-kart](https://gitlab.hevs.ch/course/ElN/eln_kart_sodimm200.git) +* [ELN-display](https://gitlab.hevs.ch/course/ElN/eln_display.git) + +**SVN Repos** +* [CanSat](https://repos.hevs.ch/svn/eda/VHDL/labs/CanSat) (TODO) :rotating_light: +* [ELN_support](https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_support) (TODO) :rotating_light: +* [EPTM_AudioAmp](https://repos.hevs.ch/svn/eda/VHDL/labs/AudioAmp) (TODO) :rotating_light: +* [EPTM_Radio](https://repos.hevs.ch/svn/eda/VHDL/labs/EPTM_radio) (TODO) :rotating_light: +* ... + +### Files +**Linux** +* ``changeDefaultViews.bash`` - Changes RTL <=> studentVersion + * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` + * Usage master => student: ``changeDefaultViews.bash -v -a master@version -n student@version`` + * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` + * Usage student => master: ``changeDefaultViews.bash -v -a student@version -n master@version`` + * Note: use the ``-r`` otion to also delete the specified actual_view +* ``cleanGenerated.bash`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bash`` +* ``hdlDesigner.bash`` - Main script for starting HDL-Designer +* ``deployLibs.bash`` - Execution from eln_libs repo, copy required libraries to student repo and commit/push it. + * Usage: ``./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployLibsAll.bash`` - Execution from eln_libs repo, copy required libraries to all student repo's and commit/push it. + * Usage: ``./Scripts/deployLibsAll.bash`` +* ``deployLab.bash`` - Execution from Laborepo, copy required laboratory files to student repo and commits/push it. + * Usage: ``./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScripts.bash`` - Copy required scripts to student repo and commits/push it. + * Usage: ``./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScriptsAll.bash`` - Execution from eln_scripts repo, copy required scripts to all student repo's and commit/push it. + * Usage: ``./deployScriptsAll.bash`` + +**Windows** +* ``cleanGenerated.bat`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bat`` +* ``cleanScratch.bat`` - Delete scratch directory + * Usage: +``` bash +set SCRATCH_DIR=C:\temp\eda\%username% +./cleanScratch.bat +``` + +* ``hdlDesigner.bat`` - Main script for starting HDL-Designer +* ``searchPaths.bat`` - Search for required Libraries and tools + * Usage: +``` bash +:: Define required Tools to be present +set REQUIRE_LIBS=1 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=1 +set REQUIRE_LIBERO=0 +set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries +set HDS_HOME=C:\eda\MentorGraphics\HDS +set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +set ISE_VERSION=14.7 +set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +set LIBERO_HOME=C:\eda\Microsemi\Libero +set design_name=eln_labs +./searchPaths.bat +``` + +**Perl Scripts** +Perl scripts are used to launch different tasks from HDL-Designer +* ``trimLibs.pl`` - Comment regular libraries in an concatenated file + * Parameter : ``trimlibs.pl `` +* ``update_ise.pl`` - + * Parameter : ``update_ise.pl `` +* ``update_libero.pl`` - + * Parameter : ``update_libero.pl `` +* ``start_libero.pl`` - + * Parameter : ``start_libero.pl `` + +## How To Use +[(Back to top)](#table-of-contents) + +To clone and run this application, you'll need [Git](https://git-scm.com) installed on your computer. +This repo is normally used as submodule to the laboratories and projects. + +To deploy the studentVersion to github cd to root of Labor master repo: +```bash +cd eln_labs +./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLab.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLab.bash -v -p isc-eln-labs -r https://github.com/hei-isc-eln/eln-labs.git + +cd sem_labs +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 01-WaveformGenerator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 02-SplineInterpolator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 03-DigitalToAnalogConverter +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 04-Lissajous +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 05-Morse +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 06-07-08-09-SystemOnChip +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 10-PipelinedOperators + +cd eln_chrono +./Scripts/deployLab.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git + +cd eln_cursor +./Scripts/deployLab.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git + +cd eln-display +./Scripts/deployLab.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git + +cd eln-kart +./Scripts/deployLab.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +``` + +To deploy the Libraries to github cd to root of Libs master repo: +```bash +./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./Scripts/deployLibs.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./Scripts/deployLibs.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./Scripts/deployLibs.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./Scripts/deployLibs.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./Scripts/deployLibs.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./Scripts/deployLibs.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./Scripts/deployLibs.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +./Scripts/deployLibs.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./Scripts/deployLibsAll.bash +``` + +To deploy the Scripts to github cd root of Scripts master Repo +```bash +./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./deployScripts.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./deployScripts.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./deployScripts.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./deployScripts.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./deployScripts.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./deployScripts.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./deployScripts.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./deployScripts.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./deployScripts.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-display.git +./deployScripts.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./deployScriptsAll.bash +``` + +
+![eln labs deployment](img/eln_labs_deployment-staff.png) +
+ +### Download +```bash +# Clone repo including submodules +git clone --recursive +``` + +### Pull changes repo and submodules +```bash +# Pull all changes in the repo including changes in the submodules (of given commit) +git pull --recurse-submodules +``` + +#### Update to latest commit +Update submodule to latest commit and update parentrepo +```bash +# Update submodule to latest commit +git submodule update --remote --merge + +# Afterwared you need to commit in the parentrepo the new pointer to the new commit in the submodule +git commit -am "Update submodule to latest commit" +``` + +### Add submodule +If the folder ``Scripts`` already exists, delete it and commit these changes. +Add submodule and define the master branch as the one you want to track +```bash +git submodule add -b master +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_scripts.git Scripts +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_libs.git Libs + +git submodule init + +git submodule update +``` + +## Credits +[(Back to top)](#table-of-contents) +* COF +* PRC +* ZAS +* AMA + +## License +[(Back to top)](#table-of-contents) + +:copyright: [All rights reserved](LICENSE) + +--- + +## Find us on +> Website [hevs.ch](https://www.hevs.ch)  ·  +> LinkedIn [HES-SO Valais-Wallis](https://www.linkedin.com/groups/104343/)  ·  +> Youtube [HES-SO Valais-Wallis](https://www.youtube.com/user/HESSOVS) +> Twitter [@hessovalais](https://twitter.com/hessovalais)  ·  +> Facebook [@hessovalais](https://www.facebook.com/hessovalais)  ·  \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/changeDefaultViews.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/changeDefaultViews.bash new file mode 100644 index 0000000..be6fa62 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/changeDefaultViews.bash @@ -0,0 +1,94 @@ +#!/bin/bash + +#================================================================================ +# changeDefaultViews.bash - change HDL Project views +# * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` +# * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` +# * Usage: add ``-r`` for deleting the specified actual view **dangerous** +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +project_directory='' +actual_view='masterVersion' +new_view='studentVersion' + +usage='Usage: changeDefaultViews.bash [-p projectDir] [-r] [-v] [-h]' +while getopts 'p:a:n:rvh' options; do + case $options in + p ) project_directory=$OPTARG;; + a ) actual_view=$OPTARG;; + n ) new_view=$OPTARG;; + r ) delete_actual_view=1;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done +if [ -z "$project_directory" ]; then + project_directory="$base_directory" +else + project_directory="$base_directory/$project_directory" +fi + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Changing default views for HDL Designer" + echo "${INDENT}in $project_directory" + echo "${INDENT}from $actual_view to $new_view" + if [ -n "$delete_actual_view" ] ; then + echo "Delete all $actual_view in $project_directory" + fi +fi + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Change views in configuration files +# +find $project_directory -type f -name '*._epf' \ + | xargs sed -i "s/$actual_view/$new_view/g" + +#------------------------------------------------------------------------------- +# Remove all acutal views File +# +if [ -n "$delete_actual_view" ] ; then + project_directory=`realpath $project_directory` + echo $project_directory + echo "Delete $actual_view" + find $project_directory/ -type f -iname "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -iname "*$actual_view*" -exec rm {} \; + # For HDL Designer file naming convention + # making uppercase letters to @lowercase masterVersion = master@version + actual_view="$(sed -E s/\([A-Z]\)/@\\L\\1/g <<< $actual_view)" + find $project_directory/ -type f -name "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -name "*$actual_view*" -exec rm {} \; + +fi + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash new file mode 100644 index 0000000..ca088c6 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLab.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLab.bash new file mode 100644 index 0000000..10652b0 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLab.bash @@ -0,0 +1,559 @@ +#!/bin/bash + +#================================================================================ +# deployLab.bash - updates github repos for individual labos +# Example usage 01: ./Scripts/deployLab.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 02: ./Scripts/deployLab.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 03: ./Scripts/deployLab.bash -v -p isc-did-labs -r https://github.com/hei-isc-eln/did-labs.git +# Example usage 04: ./Scripts/deployLab.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 05: ./Scripts/deployLab.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 06: ./Scripts/deployLab.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 07: ./Scripts/deployLab.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 08: ./Scripts/deployLab.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 09: ./Scripts/deployLab.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git + +# Example usage 10: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 11: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 12: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +# Example usage 13: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +# Example usage 14: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +# Example usage 15: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +# Example usage 16: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +# Example usage 17: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +# Example usage 18: ./Scripts/deployLab.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -s 1 +# Example usage 19: ./Scripts/deployLab.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='synd-did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +dir='01-StepperMotor' +sourceDirUp=0 + +usage='Usage: deployLab.bash [-p projectName] [-r repourl] [-d directory] [-s sourceDirUp] [-v] [-h]' +while getopts 'p:r:d:s:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) dir=$OPTARG;; + s ) sourceDirUp=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Laboratory for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "${INDENT}in $dir" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +repo_dest=`realpath "./"` +repo_source="./" +# If Scripts folder is at root of project, needs to get up 3 times (scripts, project name, tmp) +# If more is needed (i.e. see car-labs structure), can be added with -s switch +for ((i=0;i<$sourceDirUp+3;i++)); do + repo_source="$repo_source/.." +done +repo_source=`realpath "$repo_source"` + +echo "Update files in student repo $project" +# Copy needed files per project +if [ "$project" == "synd-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "ete-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "isc-did-labs" ]; then + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "car-labs" ]; then + # bem + echo "copy $repo_source/bem" + cp -ar "$repo_source/bem" ./ + # isa + echo "copy $repo_source/isa" + cp -ar "$repo_source/isa" ./ + # heirv32_sc + mkdir -p heirv32_sc + # copy root files except some specific ones + find $repo_source/hdl -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest/heirv32_sc \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source/hdl -maxdepth 1 -type d ) + do + if [[ "$repo_source/hdl" != "$folder" && "$repo_source/hdl/.git" != "$folder" && "$repo_source/hdl/Libs" != "$folder" && "$repo_source/hdl/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder heirv32_sc/ + else + echo "skip $folder" + fi + done + + rm -v -f heirv32_sc/Board/concat/concatenated.vhd + rm -v -f heirv32_sc/Board/concat/car-labs.vhd + + rm -v -f heirv32_sc/HEIRV32/hdl/ALU_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/extend_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/hds/alu@decoder + rm -v -f heirv32_sc/HEIRV32/hds/_aludecoder._epf + + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/SingleCycle/hds/main@decoder + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hds/_maindecoder._epf + + rm -v -f heirv32_sc/Simulation/empty_ram.txt + +elif [ "$project" == "car-heirv" ]; then + # heirv32_mc + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source/" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + + rm -v -f ./Board/concat/concatenated.vhd + rm -v -f ./Board/concat/car-labs.vhd + + rm -v -f ./HEIRV32/hdl/ALU_rtl.vhd + rm -v -f ./HEIRV32/hdl/extend_rtl.vhd + rm -v -f ./HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f ./HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r ./HEIRV32/hds/alu@decoder + rm -v -f ./HEIRV32/hds/_aludecoder._epf + + rm -v -f ./HEIRV32/MultiCycle/hdl/instrdecoder_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_fsm.vhg + rm -v -f -r ./HEIRV32/MultiCycle/hds/instr@decoder + rm -v -f -r ./HEIRV32/MultiCycle/hds/main@f@s@m + rm -v -f ./HEIRV32/MultiCycle/hds/_instrdecoder._epf + rm -v -f ./HEIRV32/MultiCycle/hds/_mainfsm._epf + + rm -v -f ./HEIRV32_test/hdl/universalTester_test.vhd + rm -v -f -r ./HEIRV32_test/hds/universal@tester + rm -v -f ./HEIRV32_test/hds/_universaltester._epf + + rm -v -f ./Simulation/code_mc_disassembled.svg + rm -v -f ./Simulation/code_mc_disassembled_labels.svg + rm -v -f ./Simulation/code_mc_ghidra_labels.png + rm -v -f ./Simulation/empty_ram.txt + + #search='design_root = Board.ebs2_sc(struct)ebs2_sc/struct.bd' + #replace='design_root = Board.ebs2_mc(struct)ebs2_mc/struct.bd' + #sed -i "s/$search/$replace" Prefs/hds.hdp + +elif [ "$project" == "ele_labs" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "sem-labs" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/01-WaveformGenerator/Scripts" != "$folder" && "$repo_source/02-SplineInterpolator/Scripts" != "$folder" && "$repo_source/03-DigitalToAnalogConverter/Scripts" != "$folder" && "$repo_source/04-Lissajous/Scripts" != "$folder" && "$repo_source/05-Morse/Scripts" != "$folder" && "$repo_source/06-07-08-09-SystemOnChip/Scripts" != "$folder" && "$repo_source/10-PipelinedOperators/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for sem-labs $dir" + + if [ "$dir" == "01-WaveformGenerator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "02-SplineInterpolator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "03-DigitalToAnalogConverter" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "04-Lissajous" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "05-Morse" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "06-07-08-09-SystemOnChip" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "10-PipelinedOperators" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-cursor" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-cursor" + rm -v -f ./Cursor/hdl/amplitudeControl_RTL.vhd + rm -v -f ./Cursor/hdl/bridgeControl_RTL.vhd + rm -v -f ./Cursor/hdl/decelerationPositions_RTL.vhd + rm -v -f ./Cursor/hdl/divider_RTL.vhd + rm -v -f ./Cursor/hdl/findDistance_RTL1.vhd + rm -v -f ./Cursor/hdl/positionCounter_RTL.vhd + rm -v -f ./Cursor/hdl/pulseWidthModulator_RTL.vhd + rm -v -f ./Cursor/hds/_amplitudecontrol._epf + rm -v -f ./Cursor/hds/_bridgecontrol._epf + rm -v -f ./Cursor/hds/_control._epf + rm -v -f ./Cursor/hds/_decelerationpositions._epf + rm -v -f ./Cursor/hds/_divider._epf + rm -v -f ./Cursor/hds/_positioncounter._epf + rm -v -f ./Cursor/hds/_pulsewidthmodulator._epf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationpositions_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationPositions_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_findDistance_RTL1.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positioncounter_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positionCounter_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulsewidthmodulator_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulseWidthModulator_RTL.vhd._fpf + rm -v -f -r ./Cursor/hds/amplitude@control + rm -v -f -r ./Cursor/hds/bridge@control + rm -v -f -r ./Cursor/hds/control + rm -v -f -r ./Cursor/hds/deceleration@positions + rm -v -f -r ./Cursor/hds/divider + rm -v -f -r ./Cursor/hds/position@counter + rm -v -f -r ./Cursor/hds/pulse@width@modulator + rm -v -f -r ./Cursor/hds/rising@detector + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-cursor.vhd + +elif [ "$project" == "did-chrono" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-chrono" + rm -v -f ./Chronometer/hdl/coilControl_RTL.vhd + rm -v -f ./Chronometer/hdl/divider1Hz_RTL.vhd + rm -v -f ./Chronometer/hdl/tickLengthCounter_RTL.vhd + rm -v -f ./Chronometer/hdl/lcdDisplay_masterVersion.vhd + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_control._epf + rm -v -f ./Chronometer/hds/_divider1hz._epf + rm -v -f ./Chronometer/hds/_ticklengthcounter._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilcontrol_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilControl_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1hz_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1Hz_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_ticklengthcounter_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_tickLengthCounter_RTL.vhd._fpf + rm -v -f -r ./Chronometer/hds/coil@control/ + rm -v -f -r ./Chronometer/hds/control/ + rm -v -f -r ./Chronometer/hds/divider1@hz/ + rm -v -f -r ./Chronometer/hds/rising@detector/ + rm -v -f -r ./Chronometer/hds/tick@length@counter/ + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-chrono.vhd + +elif [ "$project" == "did-kart-ebs2" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs2 $dir" + + if [ "$dir" == "01-StepperMotor" ]; then + rm -v -f ./01-StepperMotor/StepperMotor/hdl/angleDifference_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/coilControl_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/stepperCounter_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hds/angle@control/master@version.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_shift@reg.bd + elif [ "$dir" == "02-DcMotor" ]; then + rm -v -f ./02-DcMotor/DcMotor/hdl/dcMotorPwm_RTL.vhd + elif [ "$dir" == "03-Sensors" ]; then + rm -v -f ./03-Sensors/Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./03-Sensors/Sensors/hdl/ultrasoundRanger_RTL.vhd + elif [ "$dir" == "04-Controller" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-kart-ebs3" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs3" + rm -v -f ./DcMotor/hdl/dcMotorPwm_RTL.vhd + rm -v -f ./Kart_test/hdl/txFIFO_tester_test.vhd + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tb/ + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tester/ + rm -v -f ./Kart_test/hds/_txfifo_tb._epf + rm -v -f ./Kart_test/hds/_txfifo_tester._epf + rm -v -f -r ./Kart_test/hds/kart@controller_full_tb/ + rm -v -f ./Kart_test/hds/_kartcontroller_full_tb._epf + rm -v -f ./Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./Sensors/hdl/ultrasoundRanger_RTL.vhd + rm -v -f ./Stepper/hdl/angleDifference_RTL.vhd + rm -v -f ./Stepper/hdl/coilControl_RTL.vhd + rm -v -f ./Stepper/hdl/stepperCounter_RTL.vhd + rm -v -f ./Stepper/hds/angle@control/master@version.bd + rm -v -f ./Stepper/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./Stepper/hds/coil@control/master@version_shift@reg.bd + rm -v -f ./Stepper_test/hdl/stepperMotorRegisters_tester_test.vhd + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tb/ + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tester/ + rm -v -f ./Stepper_test/hds/_steppermotorregisters_tb._epf + rm -v -f ./Simulation/Kart/UVM/uvmCommands.txt + rm -v -f ./Simulation/Kart/kartUVM.do + rm -v -f ./Simulation/Kart/txFIFO.do + rm -v -f ./Simulation/Stepper/stepperMotorRegisters.do + rm -v -f -r ./Simulation/UART/ + rm -v -f -r ./UART_test/ + + rm -v -f ./Board/concat/*.vhd + find ./Board/libero/designer/ ! \( -name "*.prjx" -o -name "*.adb" -o -name "*.ide_des" -o -name "*.pdb" -o -name "*_syn.prj" \) -type f -exec rm -v -f -r {} + + rm -v -f -r ./Documentation/ + rm -v -f -r ./CommandInterpreter/src/ + +elif [ "$project" == "did-synchro" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-synchro" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-synchro.vhd + +elif [ "$project" == "did-inverter" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-inverter" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-inverter.vhd + +elif [ "$project" == "did-display" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-display" + find ./Board/ise/ -name "*.mcs" -type f -exec rm -v -f {} + + rm -v -f -r ./Display/concat/ + find ./Display/hdl/ -name "*.vhg" -type f -exec rm -v -f {} + + rm -v -f ./Display/hdl/test_pattern_calculated_rtl.vhd + rm -v -f ./Display/hdl/vgaDataCreator_rgb.vhd + rm -v -f ./Display/hdl/vgaDataSelector_rtl.vhd + rm -v -f ./Display/hds/display@circuit/master@version.bd + rm -v -f -r ./Display/hds/vga@data@calculated/ + rm -v -f -r ./Display/hds/vga@data@selector/ + + rm -v -f -r ./Display_test/concat/ + + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-display.vhd + +elif [ "$project" == "eln_support" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_radio" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_audioamp" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "cansat" ]; then + echo "Error: Not implemented yet" +fi + +echo "Source taken from $repo_source to $repo_dest" + +#------------------------------------------------------------------------------- +# change from masterVersion to studentVersion and delete all masterVersion +# +if [ "$project" == "synd-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "ete-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "isc-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +else + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a master@version -n student@version -r +fi + +# add/commit/push changes to student repo +git add -A +git commit -a -m "$DATE: Automatic Laboratory Update with ``deployLab.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +echo "Delete tmp directory" +cd .. +pwd +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibs.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibs.bash new file mode 100644 index 0000000..3498c2b --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibs.bash @@ -0,0 +1,320 @@ +#!/bin/bash + +#================================================================================ +# deployLibs.bash - updates github repos for individual labos +# indend to push libs from [DiD-libs](https://gitlab.hevs.ch/course/did/did-libs.git) +# Example usage 1: ./Scripts/deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +# Example usage 12: ./Scripts/deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' + +usage='Usage: deployLibs.bash [-p projectName] [-r repourl] [-v] [-h]' +while getopts 'p:r:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Libraries for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_dest=`realpath "./Libs"` +library_source=`realpath "./../../.."` +mkdir -p $library_dest + +# Copy needed libraries per project +echo "Update files in student repo $project" +if [ "$project" == "synd-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "ete-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "isc-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "car-labs" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + library_dest=`realpath "./heirv32_sc/Libs"` + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "car-heirv" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "ele_labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, Memory, Modulation, NanoBlaze" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/Modulation" "$library_dest/" + cp -ar "$library_source/Modulation_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "sem-labs" ]; then + echo " Copy libraries: Common, RS232, AhbLite, Memory, RiscV, NanoBlaze" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RiscV" "$library_dest/" + cp -ar "$library_source/RiscV_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "did-cursor" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "did-chrono" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + #cp -ar "$library_source/RS232" "$library_dest/" + #cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs2" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs3" ]; then + echo " Copy libraries: Common, Gates, I2C, Memory, RS232, IO, Sequential, UVM" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/UVM" "$library_dest/" + cp -ar "$library_source/UVM_test" "$library_dest/" +elif [ "$project" == "did-synchro" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-inverter" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Cordic" "$library_dest/" + cp -ar "$library_source/Cordic_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "eln_support" ]; then + echo "Nothing todo, no Libararies needed" +elif [ "$project" == "did-display" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "eptm_radio" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" +elif [ "$project" == "eptm_audioamp" ]; then + echo " Copy libraries: AD_DA, Common, Filter" + cp -ar "$library_source/AD_DA" "$library_dest/" + cp -ar "$library_source/AD_DA_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Filter" "$library_dest/" + cp -ar "$library_source/Filter_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "cansat" ]; then + echo " Copy libraries: AhbLite, AhbLiteComponents, Common, Commandline, Memory, NanoBlaze, RS232" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Commandline" "$library_dest/" + cp -ar "$library_source/Commandline_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Library Update with ``deployLibs.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibsAll.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibsAll.bash new file mode 100644 index 0000000..46c6c3c --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployLibsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployLibsAll.bash - updates github repos for all labo's at once +# indend to push libs from [eda_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployLibs.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +./deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deploySEmLabs.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deploySEmLabs.bash new file mode 100644 index 0000000..b36ba70 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deploySEmLabs.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#================================================================================ +# deployLabsAll.bash - updates github repos for all labo's at once +# indend to push labs from [sem-labs](https://gitlab.hevs.ch/course/SEm/hd-labs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + + +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScripts.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScripts.bash new file mode 100644 index 0000000..a91e55b --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScripts.bash @@ -0,0 +1,331 @@ +#!/bin/bash + +#================================================================================ +# deployScripts.bash - updates github repos for individual labos +# indend to push scripts from [DiD-scripts](https://gitlab.hevs.ch/course/did/did-scripts.git) +# Example usage 1: ./Scripts/deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +# Example usage 12: ./Scripts/deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory" + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +destdir='' + +usage='Usage: deployScripts.bash [-p projectName] [-r repourl] [-d destdir] [-v] [-h]' +while getopts 'p:r:d:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) destdir=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Scripts for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_source=`realpath "./../.."` + +# DiD Kart (EBS2 version) has a different project structure +if [ "$project" == "did-kart-ebs2" ]; then + # Copy needed libraries per project + mkdir -p "01-StepperMotor/Scripts" + library_dest=`realpath "./01-StepperMotor/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + + # Copy needed libraries per project + mkdir -p "02-DcMotor/Scripts" + library_dest=`realpath "./02-DcMotor/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "03-Sensors/Scripts" + library_dest=`realpath "./03-Sensors/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "04-Controller/Scripts" + library_dest=`realpath "./04-Controller/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + +# SEm Labs has also a different project structure +elif [ "$project" == "sem-labs" ]; then + # Copy needed libraries per project + mkdir -p "01-WaveformGenerator/Scripts" + library_dest=`realpath "./01-WaveformGenerator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "02-SplineInterpolator/Scripts" + library_dest=`realpath "./02-SplineInterpolator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "03-DigitalToAnalogConverter/Scripts" + library_dest=`realpath "./03-DigitalToAnalogConverter/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "04-Lissajous/Scripts" + library_dest=`realpath "./04-Lissajous/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "05-Morse/Scripts" + library_dest=`realpath "./05-Morse/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "06-07-08-09-SystemOnChip/Scripts" + library_dest=`realpath "./06-07-08-09-SystemOnChip/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "10-PipelinedOperators/Scripts" + library_dest=`realpath "./10-PipelinedOperators/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + +else + + if [ -n "$destdir" ]; then + mkdir -p "$destdir/Scripts" + library_dest=`realpath "$destdir/Scripts"` + else + mkdir -p "Scripts" + library_dest=`realpath "./Scripts"` + fi + + # Copy needed libraries per project + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/update_diamond.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + cp -arf "$library_source/start_diamond.pl" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Scripts Update with ``deployScripts.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +#s +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScriptsAll.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScriptsAll.bash new file mode 100644 index 0000000..bb9e937 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/deployScriptsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployScriptsAll.bash - updates github Scripts folder for all labo's at once +# indend to push scripts from [eda_scripts](https://gitlab.hevs.ch/course/ElN/eda_scripts.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployScripts.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +./deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash b/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash new file mode 100644 index 0000000..4b54b46 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat b/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..87ed140 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat @@ -0,0 +1,278 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... 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index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf b/zz-solutions/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf new file mode 100644 index 0000000..aa82986 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/zz-solutions/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd b/zz-solutions/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd new file mode 100644 index 0000000..997ee19 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd @@ -0,0 +1,4708 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_sinY" +duLibraryName "SplineInterpolator" +duName "sineGen" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +] +mwi 0 +uid 2053,0 +) +(Instance +name "I_sinX" +duLibraryName "SplineInterpolator" +duName "sineGen" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +] +mwi 0 +uid 2090,0 +) +(Instance +name "I_dacY" +duLibraryName "DigitalToAnalogConverter" +duName "DAC" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +mwi 0 +uid 2162,0 +) +(Instance +name "I_dacX" +duLibraryName "DigitalToAnalogConverter" +duName "DAC" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +mwi 0 +uid 2187,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +(EmbeddedInstance +name "eb3" +number "3" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajousGenerator" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lissajousGenerator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:47:09" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lissajous" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Lissajous" +) +(vvPair +variable "library_downstream_QuestaSimCompiler" +value "$HDS_PROJECT_DIR/../Board/work" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "library_downstream_SvAssistantInvoke" +value "$HDS_PROJECT_DIR/../Board/svassistant" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "lissajousGenerator" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajousGenerator\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable 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"" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "13:07:53" +) +(vvPair +variable "unit" +value "lissajousGenerator" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 51,0 +optionalChildren [ +*69 (SymbolBody +uid 8,0 +optionalChildren [ +*70 (CptPort +uid 52,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 72,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,17625,32000,18375" +) +tg (CPTG +uid 54,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 55,0 +va (VaSet +font "courier,9,0" +) +xt "33000,17400,35500,18300" +st "clock" +blo "33000,18100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 56,0 +va (VaSet +font "courier,8,0" +) +xt "2000,10800,19000,11700" +st "clock : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*71 (CptPort +uid 88,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 89,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,17625,48750,18375" +) +tg (CPTG +uid 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"courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *91 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,9000,6500,9900" +st "Declarations" +blo "0,9700" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,9900,3000,10800" +st "Ports:" +blo "0,10600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,15300,2500,16200" +st "User:" +blo "0,16000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,9000,7500,9900" +st "Internal User:" +blo "0,9700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,16200,2000,16200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 507,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd b/zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd new file mode 100644 index 0000000..64427cf --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE test OF lissajousGenerator_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + +END ARCHITECTURE test; diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf b/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf new file mode 100644 index 0000000..66cbfb5 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator_test/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf b/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf new file mode 100644 index 0000000..335f3fd --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom lissajousGenerator_tester_test.vhd diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf b/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf new file mode 100644 index 0000000..30e9f19 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf @@ -0,0 +1,9 @@ +ARCHITECTURES list { + {lissajousgenerator_test struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/lissajousGenerator.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ns TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseCLI 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd b/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd new file mode 100644 index 0000000..11d0420 --- /dev/null +++ b/zz-solutions/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd @@ -0,0 +1,3941 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "Lissajous_test" +duName "lissajousGenerator_tester" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 421,0 +) +(Instance +name "I_DUT" +duLibraryName "Lissajous" +duName "lissajousGenerator" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +(GiElement +name "stepX" +type "positive" +value "stepX" +) +(GiElement +name "stepY" +type "positive" +value "stepY" +) +] +mwi 0 +uid 1594,0 +) +(Instance +name "I_filtX" +duLibraryName "WaveformGenerator" +duName "lowpass" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "shiftBitNb" +type "positive" +value "lowpassShiftBitNb" +) +] +mwi 0 +uid 1612,0 +) +(Instance +name "I_filty" +duLibraryName "WaveformGenerator" +duName "lowpass" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "shiftBitNb" +type "positive" +value "lowpassShiftBitNb" +) +] +mwi 0 +uid 1699,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lissajousGenerator_test" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:48:46" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lissajous_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Lissajous_test/concat" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Lissajous_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "lissajousGenerator_test" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:48:46" +) +(vvPair +variable "unit" +value "lissajousGenerator_test" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,65000,79000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,65500,62200,65500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 115,0 +shape (Rectangle +uid 116,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "79000,61000,83000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 117,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "79200,61500,79200,61500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +uid 118,0 +shape (Rectangle +uid 119,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,63000,79000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 120,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,63500,62200,63500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +uid 121,0 +shape (Rectangle +uid 122,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,63000,62000,64000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 123,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,63500,58200,63500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*6 (CommentText +uid 124,0 +shape (Rectangle +uid 125,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "79000,62000,99000,66000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 126,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "79200,62200,93300,63400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*7 (CommentText +uid 127,0 +shape (Rectangle +uid 128,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "83000,61000,99000,62000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 129,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "83200,61500,83200,61500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +uid 130,0 +shape (Rectangle +uid 131,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,61000,79000,63000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 132,0 +va (VaSet +fg "32768,0,0" +) +xt "63350,61400,73650,62600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +uid 133,0 +shape (Rectangle +uid 134,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,64000,62000,65000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 135,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,64500,58200,64500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 136,0 +shape (Rectangle +uid 137,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,65000,62000,66000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 138,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,65500,58200,65500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 139,0 +shape (Rectangle +uid 140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,64000,79000,65000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,64500,62200,64500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 111,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "58000,61000,99000,66000" +) +oxt "14000,66000,55000,71000" +) +*12 (Blk +uid 421,0 +shape (Rectangle +uid 422,0 +va (VaSet +vasetType 1 +fg "40000,56832,65535" +) +xt "11000,52000,91000,60000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 423,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*13 (Text +uid 424,0 +va (VaSet +) +xt "11700,60200,20500,61400" +st "Lissajous_test" +blo "11700,61200" +tm "BdLibraryNameMgr" +) +*14 (Text +uid 425,0 +va (VaSet +) +xt "11700,61400,26900,62600" +st "lissajousGenerator_tester" +blo "11700,62400" +tm "BlkNameMgr" +) +*15 (Text +uid 426,0 +va (VaSet +) +xt "11700,62600,16500,63800" +st "I_tester" +blo "11700,63600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 427,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 428,0 +text (MLText +uid 429,0 +va (VaSet +) +xt "12000,64000,38200,66400" +st "signalBitNb = signalBitNb ( positive ) +clockFrequency = clockFrequency ( real ) " +) +header "" +) +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +) +) +*16 (Net +uid 1554,0 +decl (Decl +n "reset" +t "std_ulogic" +o 1 +suid 10,0 +) +declText (MLText +uid 1555,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,17400,15200,18400" +st "SIGNAL reset : std_ulogic" +) +) +*17 (Net +uid 1562,0 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 11,0 +) +declText (MLText +uid 1563,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,16400,15200,17400" +st "SIGNAL clock : std_ulogic" +) +) +*18 (SaComponent +uid 1594,0 +optionalChildren [ +*19 (CptPort +uid 1574,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1575,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "22250,39625,23000,40375" +) +tg (CPTG +uid 1576,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1577,0 +va (VaSet +) +xt "24000,39400,27400,40600" +st "clock" +blo "24000,40400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 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+(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lissajous_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Lissajous_test/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Lissajous_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "lissajousGenerator_tester" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_tester\\interface" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_tester\\interface" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) 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"version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "interface" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 86,0 +optionalChildren [ +*69 (SymbolBody +uid 8,0 +optionalChildren [ +*70 (CptPort +uid 649,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 650,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "22625,5250,23375,6000" +) +tg (CPTG +uid 651,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 652,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "22300,7000,23700,10800" +st "clock" +ju 2 +blo "23500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 653,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,62000,6800" +st "clock : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 35,0 +) +) +) +*71 (CptPort +uid 654,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 655,0 +va (VaSet +vasetType 1 +fg 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"triggerOut : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "triggerOut" +t "std_ulogic" +o 9 +suid 37,0 +) +) +) +*73 (CptPort +uid 664,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 665,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "86625,5250,87375,6000" +) +tg (CPTG +uid 666,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 667,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "86300,7000,87700,14100" +st "xLowapss" +ju 2 +blo "87500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 668,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,73500,3600" +st "xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "xLowapss" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 4 +suid 38,0 +) +) +) +*74 (CptPort +uid 669,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 670,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48625,5250,49375,6000" +) +tg (CPTG +uid 671,0 +ps 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(LogicalPort +decl (Decl +n "yLowpass" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 7 +suid 40,0 +) +) +) +*76 (CptPort +uid 679,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 680,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "50625,5250,51375,6000" +) +tg (CPTG +uid 681,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 682,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "50300,7000,51700,12000" +st "ySerial" +ju 2 +blo "51500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 683,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,62000,6000" +st "ySerial : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "ySerial" +t "std_ulogic" +o 3 +suid 41,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,95000,14000" +) +oxt "15000,6000,93000,14000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text 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(Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,46000,69000,47000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,46500,53200,46500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*85 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "28000,46000,49000,48000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "33350,46400,43650,47600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*86 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "28000,49000,32000,50000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "28200,49500,28200,49500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*87 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "28000,50000,32000,51000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "28200,50500,28200,50500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*88 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,49000,49000,50000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,49500,32200,49500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "28000,46000,69000,51000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *89 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*90 (Text +uid 49,0 +va (VaSet +font "Arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*91 (MLText +uid 50,0 +va (VaSet +) +xt "0,900,17500,4500" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL;" +tm "PackageList" +) +] +) +windowSize "59,33,1075,723" +viewArea "-500,-500,85152,57543" +cachedDiagramExtent "0,0,95000,51000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "450,2150,1450,3350" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,4000,1900" +st "Panel0" +blo "1000,1700" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "Lissajous_test" +entityName "lissajousGenerator_test" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,39000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "24750,15100,29250,16000" +st "" +blo "24750,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "24750,16000,27750,16900" +st "" +blo "24750,16700" +) +) +gi *92 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +) +xt "0,12000,12700,13200" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *93 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,7600,44400,8600" +st "User:" +blo "42000,8400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +) +xt "44000,8600,44000,8600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 697,0 +activeModelName "Symbol:GEN" +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds.hdp b/zz-solutions/04-Lissajous/Prefs/hds.hdp new file mode 100644 index 0000000..9eb87ee --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds.hdp @@ -0,0 +1,46 @@ +[Concat] +Board = $HDS_PROJECT_DIR/../Board/concat +[ModelSim] +Board = $SCRATCH_DIR/Board +DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter +DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test +Lattice = $SCRATCH_DIR/Lattice +Lissajous = $SCRATCH_DIR/Lissajous +Lissajous_test = $SCRATCH_DIR/Lissajous_test +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +Board = $HDS_PROJECT_DIR/../Board/hdl +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl +Lissajous = $HDS_PROJECT_DIR/../Lissajous/hdl +Lissajous_test = $HDS_PROJECT_DIR/../Lissajous_test/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +Board = $HDS_PROJECT_DIR/../Board/hds +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hds +Lissajous = $HDS_PROJECT_DIR/../Lissajous/hds +Lissajous_test = $HDS_PROJECT_DIR/../Lissajous_test/hds +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[hds_settings] +design_root = Board.lissajousGenerator_circuit_EBS3(masterVersion)lissajous@generator_circuit_@e@b@s3/master@version.bd +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/shared.hdp b/zz-solutions/04-Lissajous/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs b/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl b/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 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"$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] 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+"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/04-Lissajous/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_labs/04-Lissajous/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "concat_file" +second "concatenated" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +] +defaultCategoryTemplates [ +1 +"architecture.vhd" +] +defaultCategoryTemplatesPrefs [ +1 +0 +] +tasksOrder [ +"USER:Generate" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:ModelSim Flow" +"USER:Prepare for Synthesis" +"USER:Xilinx Project Navigator" +] +tasksToolbarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +"\"USER:Prepare for Synthesis\"" +"\"USER:Xilinx Project Navigator\"" +] +tasksMenubarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +] +tasksShortcutbarOrder [ +"Setup DesignChecker" +"\"USER:ModelSim Compile\"" +"\"USER:ModelSim Flow\"" +"\"USER:ModelSim Simulate\"" +"USER:Generate" +"\"USER:Prepare for Synthesis\"" +] +taskPreferences [ +(TaskPref +taskName "\"USER:Actel Place and Route\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera MegaWizard\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera SOPC Builder\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" 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"Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..ef38408 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/chronometer.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" 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"$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap 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+visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..dc45370 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6853 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ 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+processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7a0938e --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/lissajousGenerator.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/zz-solutions/04-Lissajous/Scripts/.gitlab-ci.yml b/zz-solutions/04-Lissajous/Scripts/.gitlab-ci.yml new file mode 100644 index 0000000..9d1d7af --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/.gitlab-ci.yml @@ -0,0 +1,53 @@ +stages: + - deploy + +image: alpine:latest + +scripts: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployScriptsAll.bash + - deployScripts.bash + - /*.{pl} + - when: manual + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Bash" + - apk add bash + - echo "Install Core Utils" + - apk add coreutils + - echo "Install Git" + - apk add git + - echo "Set Git credentials" + - git config --global user.email "silvan.zahno@hevs.ch" + - git config --global user.name "Silvan Zahno" + - echo "Setting up deploy-eda_scripts environment" + + script: + - bash ./deployScriptsAll.bash + +libs_trigger: + stage: deploy + rules: + - if: '$CI_COMMIT_BRANCH == $CI_DEFAULT_BRANCH' + changes: + - deployLibsAll.bash + - deployLibs.bash + - when: manual + variables: + GIT_CHECKOUT: "false" + + before_script: + - echo "install additional packages" + - apk update + - apk upgrade + - echo "Install Curl" + - apk add curl + + script: + - 'curl -X POST --fail -F token=glptt-0235c37f03e3060733df7d1151555fd0c63d0adb -F ref=master "https://gitlab.hevs.ch/api/v4/projects/762/trigger/pipeline"' diff --git a/zz-solutions/04-Lissajous/Scripts/LICENSE b/zz-solutions/04-Lissajous/Scripts/LICENSE new file mode 100644 index 0000000..fdf8bfa --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/LICENSE @@ -0,0 +1,11 @@ +All Rights Reserved + +Copyright (c) 2019 - HES-SO Valais Wallis + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/README.md b/zz-solutions/04-Lissajous/Scripts/README.md new file mode 100644 index 0000000..618a38f --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/README.md @@ -0,0 +1,238 @@ +

+
+ EDA scripts Logo +
+ Hevs EDA Scripts +
+

+ +

Common Files and Scripts for ELN Laboratories practical sessions.

+ +[![pipeline status](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/pipeline.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) +[![coverage report](https://gitlab.hevs.ch/course/ElN/eda_scripts/badges/master/coverage.svg)](https://gitlab.hevs.ch/course/ElN/eda_scripts/commits/master) + +# Table of contents + + +## Description +[(Back to top)](#table-of-contents) + +These scripts can be used as for: +**Git Repos** +* [EDA_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +* [ELN_labs](https://gitlab.hevs.ch/course/ElN/eln_labs.git) +* [SEm_exams](https://gitlab.hevs.ch/course/SEm/exams.git) +* [ELN_chrono](https://gitlab.hevs.ch/course/ElN/eln_chrono.git) +* [ELN_cursor](https://gitlab.hevs.ch/course/ElN/eln_cursor.git) +* [ELN_kart](https://gitlab.hevs.ch/course/ElN/eln_kart.git) +* [ELN_inverter](https://gitlab.hevs.ch/course/ElN/eln_inverter.git) +* [ELN_synchro](https://gitlab.hevs.ch/course/ElN/eln_synchro.git) +* [SEm_labs](https://gitlab.hevs.ch/course/SEm/sem_labs.git) +* [ELN-kart](https://gitlab.hevs.ch/course/ElN/eln_kart_sodimm200.git) +* [ELN-display](https://gitlab.hevs.ch/course/ElN/eln_display.git) + +**SVN Repos** +* [CanSat](https://repos.hevs.ch/svn/eda/VHDL/labs/CanSat) (TODO) :rotating_light: +* [ELN_support](https://repos.hevs.ch/svn/eda/VHDL/labs/ELN_support) (TODO) :rotating_light: +* [EPTM_AudioAmp](https://repos.hevs.ch/svn/eda/VHDL/labs/AudioAmp) (TODO) :rotating_light: +* [EPTM_Radio](https://repos.hevs.ch/svn/eda/VHDL/labs/EPTM_radio) (TODO) :rotating_light: +* ... + +### Files +**Linux** +* ``changeDefaultViews.bash`` - Changes RTL <=> studentVersion + * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` + * Usage master => student: ``changeDefaultViews.bash -v -a master@version -n student@version`` + * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` + * Usage student => master: ``changeDefaultViews.bash -v -a student@version -n master@version`` + * Note: use the ``-r`` otion to also delete the specified actual_view +* ``cleanGenerated.bash`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bash`` +* ``hdlDesigner.bash`` - Main script for starting HDL-Designer +* ``deployLibs.bash`` - Execution from eln_libs repo, copy required libraries to student repo and commit/push it. + * Usage: ``./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployLibsAll.bash`` - Execution from eln_libs repo, copy required libraries to all student repo's and commit/push it. + * Usage: ``./Scripts/deployLibsAll.bash`` +* ``deployLab.bash`` - Execution from Laborepo, copy required laboratory files to student repo and commits/push it. + * Usage: ``./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScripts.bash`` - Copy required scripts to student repo and commits/push it. + * Usage: ``./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git`` +* ``deployScriptsAll.bash`` - Execution from eln_scripts repo, copy required scripts to all student repo's and commit/push it. + * Usage: ``./deployScriptsAll.bash`` + +**Windows** +* ``cleanGenerated.bat`` - Deletes all intermediate files + * Usage: ``./cleanGenerated.bat`` +* ``cleanScratch.bat`` - Delete scratch directory + * Usage: +``` bash +set SCRATCH_DIR=C:\temp\eda\%username% +./cleanScratch.bat +``` + +* ``hdlDesigner.bat`` - Main script for starting HDL-Designer +* ``searchPaths.bat`` - Search for required Libraries and tools + * Usage: +``` bash +:: Define required Tools to be present +set REQUIRE_LIBS=1 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=1 +set REQUIRE_LIBERO=0 +set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries +set HDS_HOME=C:\eda\MentorGraphics\HDS +set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +set ISE_VERSION=14.7 +set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +set LIBERO_HOME=C:\eda\Microsemi\Libero +set design_name=eln_labs +./searchPaths.bat +``` + +**Perl Scripts** +Perl scripts are used to launch different tasks from HDL-Designer +* ``trimLibs.pl`` - Comment regular libraries in an concatenated file + * Parameter : ``trimlibs.pl `` +* ``update_ise.pl`` - + * Parameter : ``update_ise.pl `` +* ``update_libero.pl`` - + * Parameter : ``update_libero.pl `` +* ``start_libero.pl`` - + * Parameter : ``start_libero.pl `` + +## How To Use +[(Back to top)](#table-of-contents) + +To clone and run this application, you'll need [Git](https://git-scm.com) installed on your computer. +This repo is normally used as submodule to the laboratories and projects. + +To deploy the studentVersion to github cd to root of Labor master repo: +```bash +cd eln_labs +./Scripts/deployLab.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLab.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLab.bash -v -p isc-eln-labs -r https://github.com/hei-isc-eln/eln-labs.git + +cd sem_labs +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 01-WaveformGenerator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 02-SplineInterpolator +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 03-DigitalToAnalogConverter +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 04-Lissajous +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 05-Morse +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 06-07-08-09-SystemOnChip +./Scripts/deployLab.bash -v -p sem_labs -r sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git -d 10-PipelinedOperators + +cd eln_chrono +./Scripts/deployLab.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git + +cd eln_cursor +./Scripts/deployLab.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git + +cd eln-display +./Scripts/deployLab.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git + +cd eln-kart +./Scripts/deployLab.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +``` + +To deploy the Libraries to github cd to root of Libs master repo: +```bash +./Scripts/deployLibs.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./Scripts/deployLibs.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./Scripts/deployLibs.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./Scripts/deployLibs.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./Scripts/deployLibs.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./Scripts/deployLibs.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./Scripts/deployLibs.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./Scripts/deployLibs.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./Scripts/deployLibs.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-kart.git +./Scripts/deployLibs.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./Scripts/deployLibsAll.bash +``` + +To deploy the Scripts to github cd root of Scripts master Repo +```bash +./deployScripts.bash -v -p synd_eln_labs -r https://github.com/hei-synd-2131-eln/eln_labs.git +./deployScripts.bash -v -p ete_eln_labs -r https://github.com/hei-ete-8132-eln/eln_labs.git +./deployScripts.bash -v -p isc_eln_labs -r https://github.com/hei-isc-eln/eln-labs.git +./deployScripts.bash -v -p sem_labs -r https://github.com/hei-synd-225-sem/sem_labs.git +./deployScripts.bash -v -p eln_chrono -r https://github.com/hei-synd-2131-eln/eln_chrono.git +./deployScripts.bash -v -p eln_cursor -r https://github.com/hei-synd-2131-eln/eln_cursor.git +./deployScripts.bash -v -p eln_kart -r https://github.com/hei-synd-2131-eln/eln_kart.git +./deployScripts.bash -v -p eln_inverter -r https://github.com/hei-synd-2131-eln/eln_inverter.git +./deployScripts.bash -v -p eln_synchro -r https://github.com/hei-synd-2131-eln/eln_synchro.git +./deployScripts.bash -v -p eln-kart -r https://github.com/hei-synd-2131-eln/eln-display.git +./deployScripts.bash -v -p eln-display -r https://github.com/hei-isc-eln/eln-display.git +# or +./deployScriptsAll.bash +``` + +
+![eln labs deployment](img/eln_labs_deployment-staff.png) +
+ +### Download +```bash +# Clone repo including submodules +git clone --recursive +``` + +### Pull changes repo and submodules +```bash +# Pull all changes in the repo including changes in the submodules (of given commit) +git pull --recurse-submodules +``` + +#### Update to latest commit +Update submodule to latest commit and update parentrepo +```bash +# Update submodule to latest commit +git submodule update --remote --merge + +# Afterwared you need to commit in the parentrepo the new pointer to the new commit in the submodule +git commit -am "Update submodule to latest commit" +``` + +### Add submodule +If the folder ``Scripts`` already exists, delete it and commit these changes. +Add submodule and define the master branch as the one you want to track +```bash +git submodule add -b master +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_scripts.git Scripts +git submodule add -b master https://gitlab.hevs.ch/course/ElN/eda_libs.git Libs + +git submodule init + +git submodule update +``` + +## Credits +[(Back to top)](#table-of-contents) +* COF +* PRC +* ZAS +* AMA + +## License +[(Back to top)](#table-of-contents) + +:copyright: [All rights reserved](LICENSE) + +--- + +## Find us on +> Website [hevs.ch](https://www.hevs.ch)  ·  +> LinkedIn [HES-SO Valais-Wallis](https://www.linkedin.com/groups/104343/)  ·  +> Youtube [HES-SO Valais-Wallis](https://www.youtube.com/user/HESSOVS) +> Twitter [@hessovalais](https://twitter.com/hessovalais)  ·  +> Facebook [@hessovalais](https://www.facebook.com/hessovalais)  ·  \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/changeDefaultViews.bash b/zz-solutions/04-Lissajous/Scripts/changeDefaultViews.bash new file mode 100644 index 0000000..be6fa62 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/changeDefaultViews.bash @@ -0,0 +1,94 @@ +#!/bin/bash + +#================================================================================ +# changeDefaultViews.bash - change HDL Project views +# * Usage master => student: ``changeDefaultViews.bash -v -a masterVersion -n studentVersion`` +# * Usage student => master: ``changeDefaultViews.bash -v -a studentVersion -n masterVersion`` +# * Usage: add ``-r`` for deleting the specified actual view **dangerous** +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +project_directory='' +actual_view='masterVersion' +new_view='studentVersion' + +usage='Usage: changeDefaultViews.bash [-p projectDir] [-r] [-v] [-h]' +while getopts 'p:a:n:rvh' options; do + case $options in + p ) project_directory=$OPTARG;; + a ) actual_view=$OPTARG;; + n ) new_view=$OPTARG;; + r ) delete_actual_view=1;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done +if [ -z "$project_directory" ]; then + project_directory="$base_directory" +else + project_directory="$base_directory/$project_directory" +fi + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Changing default views for HDL Designer" + echo "${INDENT}in $project_directory" + echo "${INDENT}from $actual_view to $new_view" + if [ -n "$delete_actual_view" ] ; then + echo "Delete all $actual_view in $project_directory" + fi +fi + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Change views in configuration files +# +find $project_directory -type f -name '*._epf' \ + | xargs sed -i "s/$actual_view/$new_view/g" + +#------------------------------------------------------------------------------- +# Remove all acutal views File +# +if [ -n "$delete_actual_view" ] ; then + project_directory=`realpath $project_directory` + echo $project_directory + echo "Delete $actual_view" + find $project_directory/ -type f -iname "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -iname "*$actual_view*" -exec rm {} \; + # For HDL Designer file naming convention + # making uppercase letters to @lowercase masterVersion = master@version + actual_view="$(sed -E s/\([A-Z]\)/@\\L\\1/g <<< $actual_view)" + find $project_directory/ -type f -name "*$actual_view*" -exec echo "rm {}" \; + find $project_directory/ -type f -name "*$actual_view*" -exec rm {} \; + +fi + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bash b/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bash new file mode 100644 index 0000000..ca088c6 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bat b/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/cleanScratch.bat b/zz-solutions/04-Lissajous/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/deployLab.bash b/zz-solutions/04-Lissajous/Scripts/deployLab.bash new file mode 100644 index 0000000..10652b0 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deployLab.bash @@ -0,0 +1,559 @@ +#!/bin/bash + +#================================================================================ +# deployLab.bash - updates github repos for individual labos +# Example usage 01: ./Scripts/deployLab.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 02: ./Scripts/deployLab.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 03: ./Scripts/deployLab.bash -v -p isc-did-labs -r https://github.com/hei-isc-eln/did-labs.git +# Example usage 04: ./Scripts/deployLab.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 05: ./Scripts/deployLab.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 06: ./Scripts/deployLab.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 07: ./Scripts/deployLab.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 08: ./Scripts/deployLab.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 09: ./Scripts/deployLab.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git + +# Example usage 10: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 11: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +# Example usage 12: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +# Example usage 13: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +# Example usage 14: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +# Example usage 15: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +# Example usage 16: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +# Example usage 17: ./Scripts/deployLab.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +# Example usage 18: ./Scripts/deployLab.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -s 1 +# Example usage 19: ./Scripts/deployLab.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='synd-did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +dir='01-StepperMotor' +sourceDirUp=0 + +usage='Usage: deployLab.bash [-p projectName] [-r repourl] [-d directory] [-s sourceDirUp] [-v] [-h]' +while getopts 'p:r:d:s:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) dir=$OPTARG;; + s ) sourceDirUp=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Laboratory for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "${INDENT}in $dir" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +repo_dest=`realpath "./"` +repo_source="./" +# If Scripts folder is at root of project, needs to get up 3 times (scripts, project name, tmp) +# If more is needed (i.e. see car-labs structure), can be added with -s switch +for ((i=0;i<$sourceDirUp+3;i++)); do + repo_source="$repo_source/.." +done +repo_source=`realpath "$repo_source"` + +echo "Update files in student repo $project" +# Copy needed files per project +if [ "$project" == "synd-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "ete-did-labs" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "isc-did-labs" ]; then + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + rm -v -f ./Num/hdl/sinewaveGenerator_comb.vhd + +elif [ "$project" == "car-labs" ]; then + # bem + echo "copy $repo_source/bem" + cp -ar "$repo_source/bem" ./ + # isa + echo "copy $repo_source/isa" + cp -ar "$repo_source/isa" ./ + # heirv32_sc + mkdir -p heirv32_sc + # copy root files except some specific ones + find $repo_source/hdl -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest/heirv32_sc \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source/hdl -maxdepth 1 -type d ) + do + if [[ "$repo_source/hdl" != "$folder" && "$repo_source/hdl/.git" != "$folder" && "$repo_source/hdl/Libs" != "$folder" && "$repo_source/hdl/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder heirv32_sc/ + else + echo "skip $folder" + fi + done + + rm -v -f heirv32_sc/Board/concat/concatenated.vhd + rm -v -f heirv32_sc/Board/concat/car-labs.vhd + + rm -v -f heirv32_sc/HEIRV32/hdl/ALU_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/extend_rtl.vhd + rm -v -f heirv32_sc/HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/hds/alu@decoder + rm -v -f heirv32_sc/HEIRV32/hds/_aludecoder._epf + + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_entity.vhg + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd + rm -v -f -r heirv32_sc/HEIRV32/SingleCycle/hds/main@decoder + rm -v -f heirv32_sc/HEIRV32/SingleCycle/hds/_maindecoder._epf + + rm -v -f heirv32_sc/Simulation/empty_ram.txt + +elif [ "$project" == "car-heirv" ]; then + # heirv32_mc + # copy root files except some specific ones + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + # iterate over folders to choose what to copy + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source/" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + + rm -v -f ./Board/concat/concatenated.vhd + rm -v -f ./Board/concat/car-labs.vhd + + rm -v -f ./HEIRV32/hdl/ALU_rtl.vhd + rm -v -f ./HEIRV32/hdl/extend_rtl.vhd + rm -v -f ./HEIRV32/hdl/aludecoder_entity.vhg + rm -v -f ./HEIRV32/hdl/aluDecoder_rtl.vhd + rm -v -f -r ./HEIRV32/hds/alu@decoder + rm -v -f ./HEIRV32/hds/_aludecoder._epf + + rm -v -f ./HEIRV32/MultiCycle/hdl/instrdecoder_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_entity.vhg + rm -v -f ./HEIRV32/MultiCycle/hdl/mainfsm_fsm.vhg + rm -v -f -r ./HEIRV32/MultiCycle/hds/instr@decoder + rm -v -f -r ./HEIRV32/MultiCycle/hds/main@f@s@m + rm -v -f ./HEIRV32/MultiCycle/hds/_instrdecoder._epf + rm -v -f ./HEIRV32/MultiCycle/hds/_mainfsm._epf + + rm -v -f ./HEIRV32_test/hdl/universalTester_test.vhd + rm -v -f -r ./HEIRV32_test/hds/universal@tester + rm -v -f ./HEIRV32_test/hds/_universaltester._epf + + rm -v -f ./Simulation/code_mc_disassembled.svg + rm -v -f ./Simulation/code_mc_disassembled_labels.svg + rm -v -f ./Simulation/code_mc_ghidra_labels.png + rm -v -f ./Simulation/empty_ram.txt + + #search='design_root = Board.ebs2_sc(struct)ebs2_sc/struct.bd' + #replace='design_root = Board.ebs2_mc(struct)ebs2_mc/struct.bd' + #sed -i "s/$search/$replace" Prefs/hds.hdp + +elif [ "$project" == "ele_labs" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "sem-labs" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/01-WaveformGenerator/Scripts" != "$folder" && "$repo_source/02-SplineInterpolator/Scripts" != "$folder" && "$repo_source/03-DigitalToAnalogConverter/Scripts" != "$folder" && "$repo_source/04-Lissajous/Scripts" != "$folder" && "$repo_source/05-Morse/Scripts" != "$folder" && "$repo_source/06-07-08-09-SystemOnChip/Scripts" != "$folder" && "$repo_source/10-PipelinedOperators/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for sem-labs $dir" + + if [ "$dir" == "01-WaveformGenerator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "02-SplineInterpolator" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "03-DigitalToAnalogConverter" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "04-Lissajous" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "05-Morse" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "06-07-08-09-SystemOnChip" ]; then + echo "Info: Nothing to be deleted" + elif [ "$dir" == "10-PipelinedOperators" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-cursor" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-cursor" + rm -v -f ./Cursor/hdl/amplitudeControl_RTL.vhd + rm -v -f ./Cursor/hdl/bridgeControl_RTL.vhd + rm -v -f ./Cursor/hdl/decelerationPositions_RTL.vhd + rm -v -f ./Cursor/hdl/divider_RTL.vhd + rm -v -f ./Cursor/hdl/findDistance_RTL1.vhd + rm -v -f ./Cursor/hdl/positionCounter_RTL.vhd + rm -v -f ./Cursor/hdl/pulseWidthModulator_RTL.vhd + rm -v -f ./Cursor/hds/_amplitudecontrol._epf + rm -v -f ./Cursor/hds/_bridgecontrol._epf + rm -v -f ./Cursor/hds/_control._epf + rm -v -f ./Cursor/hds/_decelerationpositions._epf + rm -v -f ./Cursor/hds/_divider._epf + rm -v -f ./Cursor/hds/_positioncounter._epf + rm -v -f ./Cursor/hds/_pulsewidthmodulator._epf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_amplitudeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgecontrol_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_bridgeControl_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationpositions_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_decelerationPositions_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_divider_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_findDistance_RTL1.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positioncounter_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_positionCounter_RTL.vhd._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulsewidthmodulator_entity.vhg._fpf + rm -v -f ./Cursor/hds/.hdlsidedata/_pulseWidthModulator_RTL.vhd._fpf + rm -v -f -r ./Cursor/hds/amplitude@control + rm -v -f -r ./Cursor/hds/bridge@control + rm -v -f -r ./Cursor/hds/control + rm -v -f -r ./Cursor/hds/deceleration@positions + rm -v -f -r ./Cursor/hds/divider + rm -v -f -r ./Cursor/hds/position@counter + rm -v -f -r ./Cursor/hds/pulse@width@modulator + rm -v -f -r ./Cursor/hds/rising@detector + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-cursor.vhd + +elif [ "$project" == "did-chrono" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-chrono" + rm -v -f ./Chronometer/hdl/coilControl_RTL.vhd + rm -v -f ./Chronometer/hdl/divider1Hz_RTL.vhd + rm -v -f ./Chronometer/hdl/tickLengthCounter_RTL.vhd + rm -v -f ./Chronometer/hdl/lcdDisplay_masterVersion.vhd + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_control._epf + rm -v -f ./Chronometer/hds/_divider1hz._epf + rm -v -f ./Chronometer/hds/_ticklengthcounter._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/_coilcontrol._epf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilcontrol_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_coilControl_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_control_fsm.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1hz_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_divider1Hz_RTL.vhd._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_ticklengthcounter_entity.vhg._fpf + rm -v -f ./Chronometer/hds/.hdlsidedata/_tickLengthCounter_RTL.vhd._fpf + rm -v -f -r ./Chronometer/hds/coil@control/ + rm -v -f -r ./Chronometer/hds/control/ + rm -v -f -r ./Chronometer/hds/divider1@hz/ + rm -v -f -r ./Chronometer/hds/rising@detector/ + rm -v -f -r ./Chronometer/hds/tick@length@counter/ + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-chrono.vhd + +elif [ "$project" == "did-kart-ebs2" ]; then + mkdir -p $dir + repo_dest=`realpath "./$dir/"` + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder $repo_dest + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs2 $dir" + + if [ "$dir" == "01-StepperMotor" ]; then + rm -v -f ./01-StepperMotor/StepperMotor/hdl/angleDifference_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/coilControl_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hdl/stepperCounter_RTL.vhd + rm -v -f ./01-StepperMotor/StepperMotor/hds/angle@control/master@version.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./01-StepperMotor/StepperMotor/hds/coil@control/master@version_shift@reg.bd + elif [ "$dir" == "02-DcMotor" ]; then + rm -v -f ./02-DcMotor/DcMotor/hdl/dcMotorPwm_RTL.vhd + elif [ "$dir" == "03-Sensors" ]; then + rm -v -f ./03-Sensors/Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./03-Sensors/Sensors/hdl/ultrasoundRanger_RTL.vhd + elif [ "$dir" == "04-Controller" ]; then + echo "Info: Nothing to be deleted" + fi + +elif [ "$project" == "did-kart-ebs3" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-kart-ebs3" + rm -v -f ./DcMotor/hdl/dcMotorPwm_RTL.vhd + rm -v -f ./Kart_test/hdl/txFIFO_tester_test.vhd + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tb/ + rm -v -f -r ./Kart_test/hds/tx@f@i@f@o_tester/ + rm -v -f ./Kart_test/hds/_txfifo_tb._epf + rm -v -f ./Kart_test/hds/_txfifo_tester._epf + rm -v -f -r ./Kart_test/hds/kart@controller_full_tb/ + rm -v -f ./Kart_test/hds/_kartcontroller_full_tb._epf + rm -v -f ./Sensors/hdl/hallCounters_RTL.vhd + rm -v -f ./Sensors/hdl/ultrasoundRanger_RTL.vhd + rm -v -f ./Stepper/hdl/angleDifference_RTL.vhd + rm -v -f ./Stepper/hdl/coilControl_RTL.vhd + rm -v -f ./Stepper/hdl/stepperCounter_RTL.vhd + rm -v -f ./Stepper/hds/angle@control/master@version.bd + rm -v -f ./Stepper/hds/coil@control/master@version_counter@demux.bd + rm -v -f ./Stepper/hds/coil@control/master@version_shift@reg.bd + rm -v -f ./Stepper_test/hdl/stepperMotorRegisters_tester_test.vhd + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tb/ + rm -v -f -r ./Stepper_test/hds/stepper@motor@registers_tester/ + rm -v -f ./Stepper_test/hds/_steppermotorregisters_tb._epf + rm -v -f ./Simulation/Kart/UVM/uvmCommands.txt + rm -v -f ./Simulation/Kart/kartUVM.do + rm -v -f ./Simulation/Kart/txFIFO.do + rm -v -f ./Simulation/Stepper/stepperMotorRegisters.do + rm -v -f -r ./Simulation/UART/ + rm -v -f -r ./UART_test/ + + rm -v -f ./Board/concat/*.vhd + find ./Board/libero/designer/ ! \( -name "*.prjx" -o -name "*.adb" -o -name "*.ide_des" -o -name "*.pdb" -o -name "*_syn.prj" \) -type f -exec rm -v -f -r {} + + rm -v -f -r ./Documentation/ + rm -v -f -r ./CommandInterpreter/src/ + +elif [ "$project" == "did-synchro" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-synchro" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-synchro.vhd + +elif [ "$project" == "did-inverter" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-inverter" + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-inverter.vhd + +elif [ "$project" == "did-display" ]; then + find $repo_source -maxdepth 1 -type f \! \( -name .gitmodules -o -name .gitlab-ci.yml -o -name README.md -o -name LICENSE \) -exec cp -ar '{}' $repo_dest \; + for folder in $(find $repo_source -maxdepth 1 -type d ) + do + if [[ "$repo_source" != "$folder" && "$repo_source/.git" != "$folder" && "$repo_source/Libs" != "$folder" && "$repo_source/Scripts" != "$folder" && "$repo_source/img" != "$folder" ]] ; then + echo "copy $folder" + cp -ar $folder ./ + else + echo "skip $folder" + fi + done + echo "" + echo "Delete solutions blocs for did-display" + find ./Board/ise/ -name "*.mcs" -type f -exec rm -v -f {} + + rm -v -f -r ./Display/concat/ + find ./Display/hdl/ -name "*.vhg" -type f -exec rm -v -f {} + + rm -v -f ./Display/hdl/test_pattern_calculated_rtl.vhd + rm -v -f ./Display/hdl/vgaDataCreator_rgb.vhd + rm -v -f ./Display/hdl/vgaDataSelector_rtl.vhd + rm -v -f ./Display/hds/display@circuit/master@version.bd + rm -v -f -r ./Display/hds/vga@data@calculated/ + rm -v -f -r ./Display/hds/vga@data@selector/ + + rm -v -f -r ./Display_test/concat/ + + rm -v -f -r ./Board/concat/concatenated.vhd + rm -v -f -r ./Board/concat/did-display.vhd + +elif [ "$project" == "eln_support" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_radio" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "eptm_audioamp" ]; then + echo "Error: Not implemented yet" + +elif [ "$project" == "cansat" ]; then + echo "Error: Not implemented yet" +fi + +echo "Source taken from $repo_source to $repo_dest" + +#------------------------------------------------------------------------------- +# change from masterVersion to studentVersion and delete all masterVersion +# +if [ "$project" == "synd-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "ete-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +elif [ "$project" == "isc-did-labs" ]; then + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/did-labs" -a master@version -n student@version -r +else + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a masterVersion -n studentVersion -r + ./../../changeDefaultViews.bash -p "Scripts/tmp/$project" -a master@version -n student@version -r +fi + +# add/commit/push changes to student repo +git add -A +git commit -a -m "$DATE: Automatic Laboratory Update with ``deployLab.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +echo "Delete tmp directory" +cd .. +pwd +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd diff --git a/zz-solutions/04-Lissajous/Scripts/deployLibs.bash b/zz-solutions/04-Lissajous/Scripts/deployLibs.bash new file mode 100644 index 0000000..3498c2b --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deployLibs.bash @@ -0,0 +1,320 @@ +#!/bin/bash + +#================================================================================ +# deployLibs.bash - updates github repos for individual labos +# indend to push libs from [DiD-libs](https://gitlab.hevs.ch/course/did/did-libs.git) +# Example usage 1: ./Scripts/deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +# Example usage 12: ./Scripts/deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' + +usage='Usage: deployLibs.bash [-p projectName] [-r repourl] [-v] [-h]' +while getopts 'p:r:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Libraries for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clean current repo +# +echo "Clean parent repo from intermediate files" +./cleanGenerated.bash + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_dest=`realpath "./Libs"` +library_source=`realpath "./../../.."` +mkdir -p $library_dest + +# Copy needed libraries per project +echo "Update files in student repo $project" +if [ "$project" == "synd-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "ete-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "isc-did-labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, NanoBlaze" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/IO/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/NanoBlaze/" "$library_dest/" +elif [ "$project" == "car-labs" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + library_dest=`realpath "./heirv32_sc/Libs"` + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "car-heirv" ]; then + echo " Copy libraries: Common, Gates, Memory, Operators, Sequential" + cp -arf "$library_source/Common/" "$library_dest/" + cp -arf "$library_source/Common_test/" "$library_dest/" + cp -arf "$library_source/Gates/" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -arf "$library_source/Memory/" "$library_dest/" + cp -arf "$library_source/Operators/" "$library_dest/" + cp -arf "$library_source/Sequential/" "$library_dest/" +elif [ "$project" == "ele_labs" ]; then + echo " Copy libraries: Gates, IO, Sequential, Operators, Common, Memory, Modulation, NanoBlaze" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/Modulation" "$library_dest/" + cp -ar "$library_source/Modulation_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "sem-labs" ]; then + echo " Copy libraries: Common, RS232, AhbLite, Memory, RiscV, NanoBlaze" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RiscV" "$library_dest/" + cp -ar "$library_source/RiscV_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" +elif [ "$project" == "did-cursor" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "did-chrono" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + #cp -ar "$library_source/RS232" "$library_dest/" + #cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs2" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-kart-ebs3" ]; then + echo " Copy libraries: Common, Gates, I2C, Memory, RS232, IO, Sequential, UVM" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/I2C" "$library_dest/" + cp -ar "$library_source/I2C_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/UVM" "$library_dest/" + cp -ar "$library_source/UVM_test" "$library_dest/" +elif [ "$project" == "did-synchro" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +elif [ "$project" == "did-inverter" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Cordic" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Operators" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Cordic" "$library_dest/" + cp -ar "$library_source/Cordic_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "eln_support" ]; then + echo "Nothing todo, no Libararies needed" +elif [ "$project" == "did-display" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common, Lcd, Memory, RS232" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Lcd" "$library_dest/" + cp -ar "$library_source/Lcd_test" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" +elif [ "$project" == "eptm_radio" ]; then + echo " Copy libraries: Gates, IO, Sequential, Common" + cp -ar "$library_source/Gates" "$library_dest/" + cp -ar "$library_source/IO" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Sequential" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" +elif [ "$project" == "eptm_audioamp" ]; then + echo " Copy libraries: AD_DA, Common, Filter" + cp -ar "$library_source/AD_DA" "$library_dest/" + cp -ar "$library_source/AD_DA_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Common_test" "$library_dest/" + cp -ar "$library_source/Filter" "$library_dest/" + cp -ar "$library_source/Filter_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" +elif [ "$project" == "cansat" ]; then + echo " Copy libraries: AhbLite, AhbLiteComponents, Common, Commandline, Memory, NanoBlaze, RS232" + cp -ar "$library_source/AhbLite" "$library_dest/" + cp -ar "$library_source/AhbLite_test" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents" "$library_dest/" + cp -ar "$library_source/AhbLiteComponents_test" "$library_dest/" + cp -ar "$library_source/Common" "$library_dest/" + cp -ar "$library_source/Commandline" "$library_dest/" + cp -ar "$library_source/Commandline_test" "$library_dest/" + cp -arf "$library_source/Lattice/" "$library_dest/" + cp -ar "$library_source/Memory" "$library_dest/" + cp -ar "$library_source/Memory_test" "$library_dest/" + cp -ar "$library_source/NanoBlaze" "$library_dest/" + cp -ar "$library_source/NanoBlaze_test" "$library_dest/" + cp -ar "$library_source/RS232" "$library_dest/" + cp -ar "$library_source/RS232_test" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Library Update with ``deployLibs.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/deployLibsAll.bash b/zz-solutions/04-Lissajous/Scripts/deployLibsAll.bash new file mode 100644 index 0000000..46c6c3c --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deployLibsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployLibsAll.bash - updates github repos for all labo's at once +# indend to push libs from [eda_libs](https://gitlab.hevs.ch/course/ElN/eda_libs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployLibs.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployLibs.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployLibs.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployLibs.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployLibs.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployLibs.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployLibs.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployLibs.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployLibs.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployLibs.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployLibs.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployLibs.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git +./deployLibs.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/deploySEmLabs.bash b/zz-solutions/04-Lissajous/Scripts/deploySEmLabs.bash new file mode 100644 index 0000000..b36ba70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deploySEmLabs.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#================================================================================ +# deployLabsAll.bash - updates github repos for all labo's at once +# indend to push labs from [sem-labs](https://gitlab.hevs.ch/course/SEm/hd-labs.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + + +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 01-WaveformGenerator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 02-SplineInterpolator +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 03-DigitalToAnalogConverter +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 04-Lissajous +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 05-Morse +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 06-07-08-09-SystemOnChip +./deployLab.bash -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git -d 10-PipelinedOperators + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/deployScripts.bash b/zz-solutions/04-Lissajous/Scripts/deployScripts.bash new file mode 100644 index 0000000..a91e55b --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deployScripts.bash @@ -0,0 +1,331 @@ +#!/bin/bash + +#================================================================================ +# deployScripts.bash - updates github repos for individual labos +# indend to push scripts from [DiD-scripts](https://gitlab.hevs.ch/course/did/did-scripts.git) +# Example usage 1: ./Scripts/deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +# Example usage 2: ./Scripts/deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +# Example usage 3: ./Scripts/deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +# Example usage 4: ./Scripts/deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +# Example usage 5: ./Scripts/deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +# Example usage 6: ./Scripts/deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +# Example usage 7: ./Scripts/deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +# Example usage 8: ./Scripts/deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +# Example usage 9: ./Scripts/deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +# Example usage 10: ./Scripts/deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +# Example usage 11: ./Scripts/deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +# Example usage 12: ./Scripts/deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory" + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Parse command line options +# +project='did-labs' +repo='https://github.com/hei-synd-did/did-labs.git' +destdir='' + +usage='Usage: deployScripts.bash [-p projectName] [-r repourl] [-d destdir] [-v] [-h]' +while getopts 'p:r:d:vh' options; do + case $options in + p ) project=$OPTARG;; + r ) repo=$OPTARG;; + d ) destdir=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "-- $DATE: Deploy Scripts for Students" + echo "${INDENT}for $project" + echo "${INDENT}to $repo" + echo "" +fi + +#------------------------------------------------------------------------------- +# Clone student repo +# +# Create a tmp subdirectory if it doesn't exist +echo "Create tmp folder" +mkdir -p tmp +cd tmp + +# Get repo +echo "Clone student repo $project" +# Add login and access token to url +repo_access=$(echo $repo | sed 's/https\?:\/\///') +github_username=tschinz +github_accesstoken=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 +repo_access="https://$github_username:$github_accesstoken@${repo_access}" +git clone $repo_access +if [ "$project" == "synd-did-labs" ]; then + cd did-labs +elif [ "$project" == "ete-did-labs" ]; then + cd did-labs +elif [ "$project" == "isc-did-labs" ]; then + cd did-labs +else + cd $project +fi + +library_source=`realpath "./../.."` + +# DiD Kart (EBS2 version) has a different project structure +if [ "$project" == "did-kart-ebs2" ]; then + # Copy needed libraries per project + mkdir -p "01-StepperMotor/Scripts" + library_dest=`realpath "./01-StepperMotor/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + + # Copy needed libraries per project + mkdir -p "02-DcMotor/Scripts" + library_dest=`realpath "./02-DcMotor/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "03-Sensors/Scripts" + library_dest=`realpath "./03-Sensors/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + # Copy needed libraries per project + mkdir -p "04-Controller/Scripts" + library_dest=`realpath "./04-Controller/Scripts"` + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + + +# SEm Labs has also a different project structure +elif [ "$project" == "sem-labs" ]; then + # Copy needed libraries per project + mkdir -p "01-WaveformGenerator/Scripts" + library_dest=`realpath "./01-WaveformGenerator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "02-SplineInterpolator/Scripts" + library_dest=`realpath "./02-SplineInterpolator/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "03-DigitalToAnalogConverter/Scripts" + library_dest=`realpath "./03-DigitalToAnalogConverter/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "04-Lissajous/Scripts" + library_dest=`realpath "./04-Lissajous/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "05-Morse/Scripts" + library_dest=`realpath "./05-Morse/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "06-07-08-09-SystemOnChip/Scripts" + library_dest=`realpath "./06-07-08-09-SystemOnChip/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + + mkdir -p "10-PipelinedOperators/Scripts" + library_dest=`realpath "./10-PipelinedOperators/Scripts"` + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + +else + + if [ -n "$destdir" ]; then + mkdir -p "$destdir/Scripts" + library_dest=`realpath "$destdir/Scripts"` + else + mkdir -p "Scripts" + library_dest=`realpath "./Scripts"` + fi + + # Copy needed libraries per project + echo "Update files in student repo $project" + echo " Copy scripts for Windows" + cp -arf "$library_source/hdlDesigner.bat" "$library_dest/" + cp -arf "$library_source/cleanScratch.bat" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bat" "$library_dest/" + cp -arf "$library_source/searchPaths.bat" "$library_dest/" + echo " Copy scripts for Linux" + cp -arf "$library_source/hdlDesigner.bash" "$library_dest/" + cp -arf "$library_source/cleanGenerated.bash" "$library_dest/" + cp -arf "$library_source/generateSSHKey.bash" "$library_dest/" + echo " Copy perl scripts for HDL Designer" + cp -arf "$library_source/trimLibs.pl" "$library_dest/" + cp -arf "$library_source/update_ise.pl" "$library_dest/" + cp -arf "$library_source/update_libero.pl" "$library_dest/" + cp -arf "$library_source/update_diamond.pl" "$library_dest/" + cp -arf "$library_source/start_libero.pl" "$library_dest/" + cp -arf "$library_source/start_diamond.pl" "$library_dest/" +fi + +# add/commit/push changes to student repo +echo " Git: Add => Commit => Push" +git add -A +git commit -a -m "$DATE: Automatic Scripts Update with ``deployScripts.bash`` :shipit:" +git push origin main +cd .. + +# Delete tmp directory +cd .. +echo " Delete tmp directory" +rm -rf "./tmp" + +#------------------------------------------------------------------------------- +# Exit +#s +echo "" +echo "-- $DATE: $project updated at $repo" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/deployScriptsAll.bash b/zz-solutions/04-Lissajous/Scripts/deployScriptsAll.bash new file mode 100644 index 0000000..bb9e937 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/deployScriptsAll.bash @@ -0,0 +1,37 @@ +#!/bin/bash + +#================================================================================ +# deployScriptsAll.bash - updates github Scripts folder for all labo's at once +# indend to push scripts from [eda_scripts](https://gitlab.hevs.ch/course/ElN/eda_scripts.git) +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' +DATE=`date '+%Y-%m-%d %H:%M:%S'` + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +./deployScripts.bash -v -p synd-did-labs -r https://github.com/hei-synd-did/did-labs.git +./deployScripts.bash -v -p ete-did-labs -r https://github.com/hei-ete-did/did-labs.git +./deployScripts.bash -v -p isc-did-labs -r https://github.com/hei-isc-did/did-labs.git +./deployScripts.bash -v -p did-chrono -r https://github.com/hei-synd-did/did-chrono.git +./deployScripts.bash -v -p did-cursor -r https://github.com/hei-synd-did/did-cursor.git +#./deployScripts.bash -v -p did-kart-ebs2 -r https://github.com/hei-synd-did/did-ket-ebs2.git # repo does not exist !!! +./deployScripts.bash -v -p did-inverter -r https://github.com/hei-ete-did/did-inverter.git +./deployScripts.bash -v -p did-synchro -r https://github.com/hei-ete-did/did-synchro.git +./deployScripts.bash -v -p did-kart-ebs3 -r https://github.com/hei-synd-did/did-kart-ebs3.git +./deployScripts.bash -v -p did-display -r https://github.com/hei-isc-did/did-display.git +./deployScripts.bash -v -p sem-labs -r https://github.com/hei-synd-sem/sem-labs.git +./deployScripts.bash -v -p car-labs -r https://github.com/hei-isc-car/car-labs.git -d heirv32_sc +./deployScripts.bash -v -p car-heirv -r https://github.com/hei-isc-car/car-heirv.git + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- $DATE: ${0##*/} finished" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/generateSSHKey.bash b/zz-solutions/04-Lissajous/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bash b/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bash new file mode 100644 index 0000000..4b54b46 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bat b/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..87ed140 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/hdlDesigner.bat @@ -0,0 +1,278 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... 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z5slpcST}!$8~P7WhC{jTkZBebrDfGX>qt%S4M-;Nv$%o<= zszHu|jpJD5?qJimvJMdQpFucx+aITouUdP_+smI6qL_!#ugDh zN}&D!wbIJZ=~NM2OaCmL(JE0eo`y7Ps(3hK2h=w5YoGVQc9Ny|U|vqAtCg!0C$0W9 z0z)4AdXeNv_SWR7kuBoE1}-HG1G6qnWAer+f!zL;&369C<|K!+^zFa4BoPtmkV3iF zQ(BqSO)6r3wSmd*%x=@4aJB2a#rzbE@&+iQ{R|4!LT0YNwbSoAM{oxJ9xPNZKtbPp z%w?(0Bx7=65BoY!Rwt0`vVXq&VZlqwuh-SpTg}?pYV-GSg-yDasXuWD0a)kuw zYiJcYPers6>b%SE`M +# Parameter : start_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# V0.2 : ama 02.2023 -- Adapted for Diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Diamond +# + +if ($verbose == 1) { + print "$separator\n\n"; + print "Launching Diamond from $designerExe\n"; + print $indent, "* Project file spec: $diamondFileSpec\n\n"; + print "$separator\n\n"; +} + +system("$designerExe $diamondFileSpec"); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/start_libero.pl b/zz-solutions/03-DigitalToAnalogConverter/Scripts/start_libero.pl new file mode 100644 index 0000000..3e11301 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/start_libero.pl @@ -0,0 +1,37 @@ +#!/usr/bin/perl +# filename: start_libero.pl +# created by: Corthay Francois & Zahno Silvan +# +#------------------------------------------------------------------------------- +# +# Description: +# Starts Libero in the correct timezone for the Synplify License +# Help Parameter : +# Parameter : start_libero.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Libero +# + +if ($verbose == 1) { + print "\n"; + print "launching $designerExe\n"; + print $indent, "project file spec: $liberoFileSpec\n"; + print "$separator\n"; +} + +system("$designerExe $liberoFileSpec"); \ No newline at end of file diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/trimLibs.pl b/zz-solutions/03-DigitalToAnalogConverter/Scripts/trimLibs.pl new file mode 100644 index 0000000..efbff23 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/trimLibs.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ------------------------------------------------------------------------------ +# Changelog: +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/zz-solutions/03-DigitalToAnalogConverter/Scripts/update_diamond.pl b/zz-solutions/03-DigitalToAnalogConverter/Scripts/update_diamond.pl new file mode 100644 index 0000000..92e9076 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Scripts/update_diamond.pl @@ -0,0 +1,129 @@ +#!/usr/bin/perl +# filename: update_diamond.pl +# created by: Corthay Francois & Zahno Silvan & Amand Axel +# +#------------------------------------------------------------------------------- +# +# Description: +# Updates the file references in the .ldf Lattice project file +# and launches the Diamond project manager +# Help Parameter : +# Parameter : update_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# V0.3 : ama 02.2023 -- Adapted for diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$lpfFileSpec = $ARGV[2]; + +use File::Basename; +$diamond_dir = dirname(dirname($vhdlFileSpec)) . '/diamond/'; # get up concat and into diamond +$projectTitle = basename($diamondFileSpec, ".ldf"); + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * diamondFileSpec: $diamondFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * lpfFileSpec: $lpfFileSpec\n"; + print " * Project title: $projectTitle\n" +} + + +#------------------------------------------------------------------------------- +# Project variables +# + +$diamondWorkFileSpec = $diamondFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{DIAMOND_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n\n"; + print "Updating file specifications in $diamondFileSpec\n"; + print $indent, "temporary file spec: $diamondWorkFileSpec\n"; +} +my $line; +if ( !open(DiamondFile, $diamondFileSpec) ){ + print("\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"); + die "\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"; +} + +open(workFile, ">$diamondWorkFileSpec"); +while (chop($line = )) { + + # replace title + if ($line =~ m/ +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +# Parameter : update_libero.pl <^PDC File Spec> +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$pdcFileSpec = $ARGV[2]; + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * liberoFileSpec: $liberoFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * pdcFileSpec: $pdcFileSpec\n"; +} + + + +#------------------------------------------------------------------------------- +# Project variables +# +$liberoWorkFileSpec = $liberoFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{LIBERO_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $liberoFileSpec\n"; + print $indent, "temporary file spec: $liberoWorkFileSpec\n"; +} +my $line; + +open(LiberoFile, $liberoFileSpec) || die "couldn't open $HDLFileSpec!"; +open(workFile, ">$liberoWorkFileSpec"); +while (chop($line = )) { + # replace source path + if ($line =~ m/DEFAULT_IMPORT_LOC/i) { + $line =~ s/".*"/"$sourceDir"/; + } + # replace project path + if ($line =~ m/ProjectLocation/i) { + $line =~ s/".*"/"$projectDir"/; + } + # replace VHDL file spec + if ($line =~ m/VALUE\s".*,hdl"/i) { + $line =~ s/".*"/"$vhdlFileSpec,hdl"/; + } + # replace PDC file spec + if ($line =~ m/VALUE\s".*\.pdc,pdc"/i) { + $line =~ s/".*"/"$pdcFileSpec,pdc"/; + } + + print workFile ("$line\n"); +} + +close(workFile); +close(LiberoFile); + + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($liberoFileSpec); +rename($liberoWorkFileSpec, $liberoFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#------------------------------------------------------------------------------- +# Launch Libero +# + +#if ($verbose == 1) { +# print "\n"; +# print "launching $designerExe\n"; +# print $indent, "project file spec: $liberoFileSpec\n"; +# print "$separator\n"; +#} + +#system("$designerExe $liberoFileSpec"); diff --git a/zz-solutions/03-DigitalToAnalogConverter/Simulation/DAC.do b/zz-solutions/03-DigitalToAnalogConverter/Simulation/DAC.do new file mode 100644 index 0000000..4bbca67 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Simulation/DAC.do @@ -0,0 +1,27 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /dac_tb/reset +add wave -noupdate /dac_tb/clock +add wave -noupdate -divider {parallel to serial} +add wave -noupdate -format Analog-Step -height 100 -max 66000.0 -radix unsigned /dac_tb/parallelIn +add wave -noupdate /dac_tb/serialOut +add wave -noupdate -divider {serial to parallel} +add wave -noupdate -format Analog-Step -height 100 -max 65500.000000000007 -radix unsigned /dac_tb/lowpassOut +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {88797414 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 175 +configure wave -valuecolwidth 63 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {105 us} diff --git a/zz-solutions/03-DigitalToAnalogConverter/Simulation/sineGen.do b/zz-solutions/03-DigitalToAnalogConverter/Simulation/sineGen.do new file mode 100644 index 0000000..df337bb --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Simulation/sineGen.do @@ -0,0 +1,36 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /sinegen_tb/reset +add wave -noupdate /sinegen_tb/clock +add wave -noupdate -format Analog-Step -height 30 -max 1300.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/phase +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/triangle +add wave -noupdate -divider sinewave +add wave -noupdate -format Analog-Step -height 80 -max 43200.0 -min -32800.0 -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/sineSamples +add wave -noupdate /sinegen_tb/I_DUT/newPolynom +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/a +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/b +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/c +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/d +add wave -noupdate -format Analog-Step -height 80 -max 76000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 250 +configure wave -valuecolwidth 52 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {52589 ns} +run 50 us diff --git a/zz-solutions/03-DigitalToAnalogConverter/Simulation/waveformGen.do b/zz-solutions/03-DigitalToAnalogConverter/Simulation/waveformGen.do new file mode 100644 index 0000000..ce4b33d --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/Simulation/waveformGen.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /waveformgen_tb/reset +add wave -noupdate /waveformgen_tb/clock +add wave -noupdate /waveformgen_tb/en +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/triangle +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/polygon +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 272 +configure wave -valuecolwidth 89 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {525 us} +run 500 us diff --git a/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bash b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bash new file mode 100644 index 0000000..933ab09 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat new file mode 100644 index 0000000..bc1b2a4 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat @@ -0,0 +1,83 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +set HDS_HOME=C:\MentorGraphics\HDS_2019.2 +set MODELSIM_HOME=C:\modeltech64_2021.3\win64 +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +set LM_LICENSE_FILE=27001@mentorlm.hevs.ch + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat.bak b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat.bak new file mode 100644 index 0000000..efe9b97 --- /dev/null +++ b/zz-solutions/03-DigitalToAnalogConverter/digitalToAnalogConverter.bat.bak @@ -0,0 +1,79 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/zz-solutions/04-Lissajous/Board/concat/concatenated.vhd b/zz-solutions/04-Lissajous/Board/concat/concatenated.vhd new file mode 100644 index 0000000..eada0f5 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/concat/concatenated.vhd @@ -0,0 +1,1585 @@ +-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator_circuit_EBS3 IS + PORT( + clock : IN std_ulogic; + reset_N : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator_circuit_EBS3 ; + + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Lissajous.lissajousGenerator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:53 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator ; + + + + + +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + + + + + +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:40 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineGen IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:46 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineTable ; + + + + + +ARCHITECTURE masterVersion OF sineTable IS + + signal changeSign : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + + signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine + +begin + + changeSign <= phase(phase'high); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1) + begin + if (flipPhase xor shiftPhase) = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if (flipPhase xor shiftPhase) = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine) + begin + if (changeSign xor (flipPhase and shiftPhase)) = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSign; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.resizer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:36 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY resizer IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END resizer ; + + + + + +ARCHITECTURE masterVersion OF resizer IS + +BEGIN + + outGtIn: if resizeOut'length > resizeIn'length generate + begin + resizeOut <= shift_left( + resize( + resizeIn, + resizeOut'length + ), + resizeOut'length-resizeIn'length + ); + end generate outGtIn; + + outEqIn: if resizeOut'length = resizeIn'length generate + begin + resizeOut <= resizeIn; + end generate outEqIn; + + outLtIn: if resizeOut'length < resizeIn'length generate + begin + resizeOut <= resize( + shift_right( + resizeIn, + resizeIn'length-resizeOut'length + ), + resizeOut'length + ); + end generate outLtIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToSquare IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToSquare ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToSquare IS +BEGIN + + square <= (others => sawtooth(sawtooth'high)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToTriangle IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToTriangle ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToTriangle IS + + signal MSB: std_uLogic; + signal triangleInt: unsigned(triangle'range); + +begin + + MSB <= sawtooth(sawtooth'high); + + foldDown: process(MSB, sawtooth) + begin + if MSB = '0' then + triangleInt <= sawtooth; + else + triangleInt <= not sawtooth; + end if; + end process foldDown; + + triangle <= triangleInt(triangleInt'high-1 downto 0) & '0'; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SplineInterpolator.sineGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:42:04 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY SplineInterpolator; +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF sineGen IS + + -- Architecture declarations + constant tableAddressBitNb : positive := 3; + constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb; + constant coeffBitNb : positive := signalBitNb+4; + + -- Internal signal declarations + SIGNAL a : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL b : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL c : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL d : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_ulogic; + SIGNAL newPolynom : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT resizer + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT ( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; + FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; + FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; + FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; + FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; + FOR ALL : resizer USE ENTITY SplineInterpolator.resizer; + FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; + FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; + FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; + FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + logic1 <= '1'; + + -- HDL Embedded Text Block 3 eb3 + logic0 <= '0'; + + + -- Instance port mappings. + I_spline : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom, + d => d, + sampleOut => sineSigned, + c => c, + b => b, + a => a, + en => logic1 + ); + I_coeffs : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4, + a => a, + b => b, + c => c, + d => d, + interpolateLinear => logic0 + ); + I_shReg : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom, + sampleIn => sineSamples, + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom, + clock => clock, + reset => reset, + en => logic1 + ); + I_unsigned : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => sine, + signedIn => sineSigned + ); + I_size : resizer + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb + ) + PORT MAP ( + resizeOut => sawtooth_internal, + resizeIn => phase + ); + I_sin : sineTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sineSamples, + phase => phase + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => logic1 + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle, + sawtooth => sawtooth_internal + ); + + -- Implicit buffered output assignments + sawtooth <= sawtooth_internal; + +END struct; + + + + +-- +-- VHDL Architecture Lissajous.lissajousGenerator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:47:09 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY DigitalToAnalogConverter; +LIBRARY SplineInterpolator; + +ARCHITECTURE struct OF lissajousGenerator IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT sineGen + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; + FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + triggerOut <= squareY(squareY'high); + + -- HDL Embedded Text Block 2 eb2 + stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length); + + -- HDL Embedded Text Block 3 eb3 + stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length); + + + -- Instance port mappings. + I_dacX : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => xOut, + parallelIn => sineX, + clock => clock, + reset => reset + ); + I_dacY : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => yOut, + parallelIn => sineY, + clock => clock, + reset => reset + ); + I_sinX : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepXUnsigned, + sawtooth => OPEN, + sine => sineX, + square => OPEN, + triangle => OPEN + ); + I_sinY : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepYUnsigned, + sawtooth => OPEN, + sine => sineY, + square => squareY, + triangle => OPEN + ); + +END struct; + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY Board; +LIBRARY Lattice; +LIBRARY Lissajous; + +ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 17; + constant stepX: positive := 3; + constant stepY: positive := 4; + + -- Internal signal declarations + SIGNAL clkSys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT lissajousGenerator + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + triggerOut : OUT std_ulogic ; + xOut : OUT std_ulogic ; + yOut : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DFF USE ENTITY Board.DFF; + FOR ALL : inverterIn USE ENTITY Board.inverterIn; + FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator; + FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 5 eb5 + logic1 <= '1'; + + -- HDL Embedded Text Block 6 eb6 + logic0 <= '0'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + U_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clkSys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_main : lissajousGenerator + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + stepX => stepX, + stepY => stepY + ) + PORT MAP ( + clock => clkSys, + reset => resetSynch, + triggerOut => triggerOut, + xOut => xOut, + yOut => yOut + ); + +END masterVersion; + + + + diff --git a/zz-solutions/04-Lissajous/Board/concat/lissajous.lpf b/zz-solutions/04-Lissajous/Board/concat/lissajous.lpf new file mode 100644 index 0000000..2d14664 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/concat/lissajous.lpf @@ -0,0 +1,334 @@ +### For reference, see TN1262 / FPGA-TN-02032 +# .lpf file format is not really documented by Lattice, normally generated through Diamond + + +################ +#### sysCONFIG +################ + +# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score) +# It can also be used on paths if the TRACE should not consider the clock domain crossing +# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK JTAGPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +# Not comprehensive +# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V +# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression +# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz +# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt +# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays) +# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin +# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs) +# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull +# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program +# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL +# which bus and mode is used to load configuration (for the Lattic IDE) +# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice +# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON) +# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF) +# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family) +SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ; +IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; + +################ +#### Labs DB +################ + +### Clock and reset ### +#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ; +#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ; + +FREQUENCY PORT "clock" 100.000000 MHz ; +LOCATE COMP "clock" SITE "K16" ; +IOBUF PORT "clock" PULLMODE=NONE ; + +LOCATE COMP "reset_N" SITE "E13" ; +GSR_NET NET "resetSynch_N"; + + +### LEDs ### +LOCATE COMP "LED1" SITE "T14" ;# red +LOCATE COMP "LED2" SITE "R14" ;# green +LOCATE COMP "LED3" SITE "T15" ;# blue + + +################ +#### SODIMM-200 +################ + +### PP2 ### +LOCATE COMP "xOut" SITE "G3" ; +LOCATE COMP "yOut" SITE "E1" ; +#LOCATE COMP "" SITE "F3" ; +LOCATE COMP "triggerOut" SITE "D1" ; +#LOCATE COMP "" SITE "F4" ; +#LOCATE COMP "" SITE "C1" ; +#LOCATE COMP "" SITE "D7" ; +#LOCATE COMP "" SITE "B6" ; +#LOCATE COMP "" SITE "C7" ; +#LOCATE COMP "" SITE "A6" ; # PP2 11 +#LOCATE COMP "" SITE "D8" ; # PP2 13 +#LOCATE COMP "" SITE "B7" ; # PP2 15 +#LOCATE COMP "" SITE "C8" ; # PP2 17 +#LOCATE COMP "" SITE "A7" ; # PP2 19 +#LOCATE COMP "" SITE "E9" ; # PP2 21 +#LOCATE COMP "" SITE "A8" ; # PP2 23 +#LOCATE COMP "" SITE "D9" ; # PP2 25 + + +### PP1 ### +#LOCATE COMP "" SITE "A9" ; +#LOCATE COMP "" SITE "D10" ; +#LOCATE COMP "" SITE "A10" ; +#LOCATE COMP "" SITE "C10" ; +#LOCATE COMP "" SITE "B10" ; +#LOCATE COMP "" SITE "C12" ; +#LOCATE COMP "" SITE "B12" ; +#LOCATE COMP "" SITE "D13" ; +#LOCATE COMP "" SITE "A13" ; +#LOCATE COMP "" SITE "M5" ; # PP1 11 +#LOCATE COMP "" SITE "L5" ; # PP1 13 +#LOCATE COMP "" SITE "K5" ; # PP1 15 +#LOCATE COMP "" SITE "H5" ; # PP1 17 +#LOCATE COMP "" SITE "E8" ; # PP1 19 +#LOCATE COMP "" SITE "E5" ; # PP1 21 +#LOCATE COMP "" SITE "E6" ; # PP1 23 +#LOCATE COMP "" SITE "E7" ; # PP1 25 + + +### USB (FTDI2232HL located on the daughterboard) ### +#LOCATE COMP "TxD" SITE "A14" ; +#IOBUF PORT "TxD" SLEWRATE=FAST ; +#LOCATE COMP "RxD" SITE "B14" ; +#IOBUF PORT "RxD" PULLMODE=UP ; +#LOCATE COMP "USB_DB_RTS" SITE "B13" ; +#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_DB_CTS" SITE "C13" ; +#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ; + + + +################ +#### Extras +################ + + +### SD Flash (External SD card) ### +#LOCATE COMP "SD_DETECT" SITE "G12" ; +#IOBUF PORT "SD_DETECT" PULLMODE=UP ; + +#LOCATE COMP "SD_CMD" SITE "C15" ; +#IOBUF PORT "SD_CMD" SLEWRATE=FAST ; +#LOCATE COMP "SD_CLK" SITE "B15" ; +#IOBUF PORT "SD_CLK" SLEWRATE=FAST ; + +#LOCATE COMP "SD_DTA[0]" SITE "B16" ; +##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[1]" SITE "C16" ; +##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[2]" SITE "F12" ; +##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[3]" SITE "C14" ; +##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ; + + +### DRAM ### +#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ; +#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ; +#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ; +#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ; +#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ; +#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ; +#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ; +#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ; +#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ; +#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ; +#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ; +#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ; +#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ; +#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_BA[0]" SITE "L14" ; +#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_BA[1]" SITE "L13" ; +#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_CLK" SITE "G14" ; +#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_CKE" SITE "G16" ; +#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nRAS" SITE "M14" ; +#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCAS" SITE "K13" ; +#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nWE" SITE "N16" ; +#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCS" SITE "M15" ; + +#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ; +#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ; +#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ; +#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ; +#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ; +#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ; +#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ; +#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ; +#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ; +#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ; +#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ; +#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ; +#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ; +#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ; +#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ; +#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ; + +#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ; +#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ; +#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ; + + + + +### USB (chip located on the motherboard) ### +#LOCATE COMP "USB_MB_TX" SITE "M11" ; +#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_RX" SITE "N12" ; +#IOBUF PORT "USB_MB_RX" PULLMODE=UP ; +#LOCATE COMP "USB_MB_RTS" SITE "N11" ; +#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_CTS" SITE "M12" ; +#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ; + + +### PMOD1 ### +#LOCATE COMP "dbg_leds[16]" SITE "P1" ; +#LOCATE COMP "dbg_leds[17]" SITE "N4" ; +#LOCATE COMP "dbg_leds[18]" SITE "P2" ; +#LOCATE COMP "dbg_leds[19]" SITE "P5" ; +#LOCATE COMP "dbg_leds[20]" SITE "R1" ; +#LOCATE COMP "dbg_leds[21]" SITE "N5" ; +#LOCATE COMP "dbg_leds[22]" SITE "R2" ; +#LOCATE COMP "dbg_leds[23]" SITE "N6" ; + + +### PMOD2 ### +#LOCATE COMP "dbg_leds[24]" SITE "R3" ; +#LOCATE COMP "dbg_leds[25]" SITE "P11" ; +#LOCATE COMP "dbg_leds[26]" SITE "P12" ; +#LOCATE COMP "dbg_leds[27]" SITE "T3" ; +#LOCATE COMP "dbg_leds[28]" SITE "R4" ; +#LOCATE COMP "dbg_leds[29]" SITE "R12" ; +#LOCATE COMP "dbg_leds[30]" SITE "T13" ; +#LOCATE COMP "dbg_leds[31]" SITE "R5" ; + + +### PMOD3 ### +#LOCATE COMP "dbg_leds[8]" SITE "B2" ; +#LOCATE COMP "dbg_leds[9]" SITE "B3" ; +#LOCATE COMP "dbg_leds[10]" SITE "A4" ; +#LOCATE COMP "dbg_leds[11]" SITE "D4" ; +#LOCATE COMP "dbg_leds[12]" SITE "A2" ; +#LOCATE COMP "dbg_leds[13]" SITE "B4" ; +#LOCATE COMP "dbg_leds[14]" SITE "C3" ; +#LOCATE COMP "dbg_leds[15]" SITE "C4" ; + + +### PMOD4 ### +#LOCATE COMP "dbg_leds[0]" SITE "J4" ; +#LOCATE COMP "dbg_leds[1]" SITE "J5" ; +#LOCATE COMP "dbg_leds[2]" SITE "H4" ; +#LOCATE COMP "dbg_leds[3]" SITE "E4" ; +#LOCATE COMP "dbg_leds[4]" SITE "J3" ; +#LOCATE COMP "dbg_leds[5]" SITE "H3" ; +#LOCATE COMP "dbg_leds[6]" SITE "E3" ; +#LOCATE COMP "dbg_leds[7]" SITE "D3" ; + + +### Ethernet ### +#LOCATE COMP "ETH_CLK_EN" SITE "B1" ; +#LOCATE COMP "ETH_nRESET" SITE "C2" ; + +#LOCATE COMP "ETH_nLED_Y" SITE "F1" ; +#LOCATE COMP "ETH_nLED_G" SITE "G2" ; + +#LOCATE COMP "ETH_MDC" SITE "J1" ; +#LOCATE COMP "ETH_MDIO" SITE "H2" ; +#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ; +#LOCATE COMP "ETH_MDINT" SITE "G1" ; +#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_REF_CLK" SITE "P3" ; + +#LOCATE COMP "ETH_TX_CLK" SITE "M4" ; +#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TX_CTL" SITE "N3" ; +#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[0]" SITE "M3" ; +#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[1]" SITE "L4" ; +#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[2]" SITE "K4" ; +#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[3]" SITE "K3" ; +#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_RX_CLK" SITE "K1" ; +#LOCATE COMP "ETH_RX_CTL" SITE "K2" ; +#LOCATE COMP "ETH_RXD[0]" SITE "L1" ; +#LOCATE COMP "ETH_RXD[1]" SITE "L2" ; +#LOCATE COMP "ETH_RXD[2]" SITE "M1" ; +#LOCATE COMP "ETH_RXD[3]" SITE "M2" ; + + +### Extras ### +#LOCATE COMP "EXT[1]" SITE "P13" ; +#LOCATE COMP "EXT[2]" SITE "R13" ; +#LOCATE COMP "EXT[3]" SITE "A3" ; +#LOCATE COMP "EXT[4]" SITE "A5" ; +#LOCATE COMP "EXT[5]" SITE "B5" ; +#LOCATE COMP "EXT[6]" SITE "C5" ; +#LOCATE COMP "EXT[7]" SITE "C6" ; +#LOCATE COMP "EXT[8]" SITE "D5" ; +#LOCATE COMP "EXT[9]" SITE "D6" ; +#LOCATE COMP "EXT[10]" SITE "A11" ; +#LOCATE COMP "EXT[11]" SITE "A12" ; +#LOCATE COMP "EXT[12]" SITE "B8" ; +#LOCATE COMP "EXT[13]" SITE "B9" ; +#LOCATE COMP "EXT[14]" SITE "B11" ; +#LOCATE COMP "EXT[15]" SITE "C9" ; +#LOCATE COMP "EXT[16]" SITE "C11" ; +#LOCATE COMP "EXT[17]" SITE "D11" ; +#LOCATE COMP "EXT[18]" SITE "D12" ; +#LOCATE COMP "EXT[19]" SITE "E10" ; +#LOCATE COMP "EXT[20]" SITE "E11" ; +#LOCATE COMP "EXT[21]" SITE "E12" ; +#LOCATE COMP "EXT[22]" SITE "L3" ; +#LOCATE COMP "EXT[23]" SITE "M6" ; +#LOCATE COMP "EXT[24]" SITE "N1" ; +#LOCATE COMP "EXT[25]" SITE "P4" ; +#LOCATE COMP "EXT[26]" SITE "P6" ; +#LOCATE COMP "EXT[27]" SITE "T2" ; +#LOCATE COMP "EXT[28]" SITE "T4" ; +#LOCATE COMP "EXT[29]" SITE "E2" ; +#LOCATE COMP "EXT[30]" SITE "F2" ; +#LOCATE COMP "EXT[31]" SITE "F5" ; +#LOCATE COMP "EXT[32]" SITE "G4" ; +#LOCATE COMP "EXT[33]" SITE "G5" ; +#LOCATE COMP "EXT[34]" SITE "J2" ; diff --git a/zz-solutions/04-Lissajous/Board/concat/lissajous.ucf b/zz-solutions/04-Lissajous/Board/concat/lissajous.ucf new file mode 100644 index 0000000..b145465 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/concat/lissajous.ucf @@ -0,0 +1,19 @@ +#------------------------------------------------------------------------------- +# Clock and reset +# +NET "clock" LOC = "A10"; +NET "reset_N" LOC = "D3" | PULLUP; + +#------------------------------------------------------------------------------- +# Analog outputs +# +NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "xOut" LOC = "G4" ; +#NET "yOut" LOC = "G5" ; + +#------------------------------------------------------------------------------- +# Trigger output +# +NET "triggerOut" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "triggerOut" LOC = "D2" ; diff --git a/zz-solutions/04-Lissajous/Board/concat/lissajous.vhd b/zz-solutions/04-Lissajous/Board/concat/lissajous.vhd new file mode 100644 index 0000000..02ed33b --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/concat/lissajous.vhd @@ -0,0 +1,1585 @@ +-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator_circuit_EBS3 IS + PORT( + clock : IN std_ulogic; + reset_N : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator_circuit_EBS3 ; + + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Lissajous.lissajousGenerator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:53 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator ; + + + + + +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + + + + + +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:40 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineGen IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:46 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineTable ; + + + + + +ARCHITECTURE masterVersion OF sineTable IS + + signal changeSign : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + + signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine + +begin + + changeSign <= phase(phase'high); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1) + begin + if (flipPhase xor shiftPhase) = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if (flipPhase xor shiftPhase) = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine) + begin + if (changeSign xor (flipPhase and shiftPhase)) = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSign; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.resizer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:36 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY resizer IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END resizer ; + + + + + +ARCHITECTURE masterVersion OF resizer IS + +BEGIN + + outGtIn: if resizeOut'length > resizeIn'length generate + begin + resizeOut <= shift_left( + resize( + resizeIn, + resizeOut'length + ), + resizeOut'length-resizeIn'length + ); + end generate outGtIn; + + outEqIn: if resizeOut'length = resizeIn'length generate + begin + resizeOut <= resizeIn; + end generate outEqIn; + + outLtIn: if resizeOut'length < resizeIn'length generate + begin + resizeOut <= resize( + shift_right( + resizeIn, + resizeIn'length-resizeOut'length + ), + resizeOut'length + ); + end generate outLtIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToSquare IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToSquare ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToSquare IS +BEGIN + + square <= (others => sawtooth(sawtooth'high)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToTriangle IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToTriangle ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToTriangle IS + + signal MSB: std_uLogic; + signal triangleInt: unsigned(triangle'range); + +begin + + MSB <= sawtooth(sawtooth'high); + + foldDown: process(MSB, sawtooth) + begin + if MSB = '0' then + triangleInt <= sawtooth; + else + triangleInt <= not sawtooth; + end if; + end process foldDown; + + triangle <= triangleInt(triangleInt'high-1 downto 0) & '0'; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SplineInterpolator.sineGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:42:04 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY SplineInterpolator; +-- LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF sineGen IS + + -- Architecture declarations + constant tableAddressBitNb : positive := 3; + constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb; + constant coeffBitNb : positive := signalBitNb+4; + + -- Internal signal declarations + SIGNAL a : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL b : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL c : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL d : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_ulogic; + SIGNAL newPolynom : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT resizer + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT ( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; +-- FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; +-- FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; +-- FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; +-- FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; +-- FOR ALL : resizer USE ENTITY SplineInterpolator.resizer; +-- FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; +-- FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; +-- FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; +-- FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + logic1 <= '1'; + + -- HDL Embedded Text Block 3 eb3 + logic0 <= '0'; + + + -- Instance port mappings. + I_spline : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom, + d => d, + sampleOut => sineSigned, + c => c, + b => b, + a => a, + en => logic1 + ); + I_coeffs : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4, + a => a, + b => b, + c => c, + d => d, + interpolateLinear => logic0 + ); + I_shReg : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom, + sampleIn => sineSamples, + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom, + clock => clock, + reset => reset, + en => logic1 + ); + I_unsigned : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => sine, + signedIn => sineSigned + ); + I_size : resizer + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb + ) + PORT MAP ( + resizeOut => sawtooth_internal, + resizeIn => phase + ); + I_sin : sineTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sineSamples, + phase => phase + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => logic1 + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle, + sawtooth => sawtooth_internal + ); + + -- Implicit buffered output assignments + sawtooth <= sawtooth_internal; + +END struct; + + + + +-- +-- VHDL Architecture Lissajous.lissajousGenerator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:47:09 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY DigitalToAnalogConverter; +-- LIBRARY SplineInterpolator; + +ARCHITECTURE struct OF lissajousGenerator IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT sineGen + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; +-- FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + triggerOut <= squareY(squareY'high); + + -- HDL Embedded Text Block 2 eb2 + stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length); + + -- HDL Embedded Text Block 3 eb3 + stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length); + + + -- Instance port mappings. + I_dacX : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => xOut, + parallelIn => sineX, + clock => clock, + reset => reset + ); + I_dacY : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => yOut, + parallelIn => sineY, + clock => clock, + reset => reset + ); + I_sinX : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepXUnsigned, + sawtooth => OPEN, + sine => sineX, + square => OPEN, + triangle => OPEN + ); + I_sinY : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepYUnsigned, + sawtooth => OPEN, + sine => sineY, + square => squareY, + triangle => OPEN + ); + +END struct; + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Board; +-- LIBRARY Lattice; +-- LIBRARY Lissajous; + +ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 17; + constant stepX: positive := 3; + constant stepY: positive := 4; + + -- Internal signal declarations + SIGNAL clkSys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT lissajousGenerator + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + triggerOut : OUT std_ulogic ; + xOut : OUT std_ulogic ; + yOut : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DFF USE ENTITY Board.DFF; +-- FOR ALL : inverterIn USE ENTITY Board.inverterIn; +-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator; +-- FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 5 eb5 + logic1 <= '1'; + + -- HDL Embedded Text Block 6 eb6 + logic0 <= '0'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + U_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clkSys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_main : lissajousGenerator + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + stepX => stepX, + stepY => stepY + ) + PORT MAP ( + clock => clkSys, + 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a/zz-solutions/04-Lissajous/Board/diamond/reveal_analyze.rva b/zz-solutions/04-Lissajous/Board/diamond/reveal_analyze.rva new file mode 100644 index 0000000..4249e0e --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/diamond/reveal_analyze.rva @@ -0,0 +1,638 @@ + + + lun. 6. mars 14:29:10 2023 + + + + + + + + + + + + 1 + + 0 + 1. LFE5U-25F + 0x41111043 + true + false + + 8 + reveal_config.rvl + reveal_config.rvs + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/zz-solutions/04-Lissajous/Board/diamond/strategy.sty new file mode 100644 index 0000000..a2b5a4a --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/diamond/strategy.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zz-solutions/04-Lissajous/Board/hdl/DFF_sim.vhd b/zz-solutions/04-Lissajous/Board/hdl/DFF_sim.vhd new file mode 100644 index 0000000..cf8868a --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hdl/DFF_sim.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/zz-solutions/04-Lissajous/Board/hdl/buff_sim.vhd b/zz-solutions/04-Lissajous/Board/hdl/buff_sim.vhd new file mode 100644 index 0000000..8ad27be --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hdl/buff_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF buff IS +BEGIN + + out1 <= in1; + +END ARCHITECTURE sim; + diff --git a/zz-solutions/04-Lissajous/Board/hdl/inverterIn_sim.vhd b/zz-solutions/04-Lissajous/Board/hdl/inverterIn_sim.vhd new file mode 100644 index 0000000..fb039ac --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hdl/inverterIn_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/zz-solutions/04-Lissajous/Board/hdl/inverter_sim.vhd b/zz-solutions/04-Lissajous/Board/hdl/inverter_sim.vhd new file mode 100644 index 0000000..ca5b6b5 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hdl/inverter_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_EBS2_masterversion.vhd b/zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_EBS2_masterversion.vhd new file mode 100644 index 0000000..68a2277 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_EBS2_masterversion.vhd @@ -0,0 +1,110 @@ +-- +-- VHDL Architecture Board.lissajousGenerator_circuit.masterVersion +-- +-- Created: +-- by - zas.UNKNOWN (ZELL) +-- at - 14:16:11 02/20/2020 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.3 (Build 4) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY Board; +LIBRARY Lissajous; + +ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 17; + constant stepX: positive := 3; + constant stepY: positive := 4; + + -- Internal signal declarations + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSnch_N : std_ulogic; + SIGNAL resetSynch : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT lissajousGenerator + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + triggerOut : OUT std_ulogic ; + xOut : OUT std_ulogic ; + yOut : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DFF USE ENTITY Board.DFF; + FOR ALL : inverterIn USE ENTITY Board.inverterIn; + FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 4 eb4 + logic1 <= '1'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSnch_N + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSnch_N, + out1 => resetSynch + ); + I_main : lissajousGenerator + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + stepX => stepX, + stepY => stepY + ) + PORT MAP ( + clock => clock, + reset => resetSynch, + triggerOut => triggerOut, + xOut => xOut, + yOut => yOut + ); + +END masterVersion; diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_EBS2_masterversion.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_EBS2_masterversion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_EBS2_masterversion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_masterversion.vhg._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_masterversion.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_masterversion.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_masterversion.vhd._fpf b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_masterversion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_masterversion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_masterversion.vhg._fpf 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b/zz-solutions/04-Lissajous/Board/hds/_lissajousgenerator_circuit_ebs2._epf new file mode 100644 index 0000000..ee31fd6 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/_lissajousgenerator_circuit_ebs2._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator_circuit_@e@b@s2/master@version.bd +DEFAULT_ARCHITECTURE atom master@version +TOP_MARKER atom 1 diff --git a/zz-solutions/04-Lissajous/Board/hds/_lissajousgenerator_circuit_ebs3._epf b/zz-solutions/04-Lissajous/Board/hds/_lissajousgenerator_circuit_ebs3._epf new file mode 100644 index 0000000..260a577 --- /dev/null +++ b/zz-solutions/04-Lissajous/Board/hds/_lissajousgenerator_circuit_ebs3._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom lissajous@generator_circuit_@e@b@s3/master@version.bd +TOP_MARKER atom 1 diff --git a/zz-solutions/04-Lissajous/Board/hds/buff/symbol.sb b/zz-solutions/04-Lissajous/Board/hds/buff/symbol.sb new file mode 100644 index 0000000..f9ad06a --- /dev/null +++ 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1809,0 +va (VaSet +) +xt "46460,36700,50060,37900" +st "Board" +blo "46460,37700" +tm "BdLibraryNameMgr" +) +*44 (Text +uid 1810,0 +va (VaSet +) +xt "46460,37700,52860,38900" +st "inverterIn" +blo "46460,38700" +tm "CptNameMgr" +) +*45 (Text +uid 1811,0 +va (VaSet +) +xt "46460,38700,50460,39900" +st "I_inv2" +blo "46460,39700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1812,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1813,0 +text (MLText +uid 1814,0 +va (VaSet +) +xt "45000,37400,45000,37400" +) +header "" +) +elements [ +] +) +portVis (PortSigDisplay +disp 1 +sN 0 +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*46 (SaComponent +uid 1817,0 +optionalChildren [ +*47 (CptPort +uid 1826,0 +optionalChildren [ +*48 (Circle +uid 1831,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "22092,41546,23000,42454" +radius 454 +) +] +ps "OnEdgeStrategy" +shape (Triangle +uid 1827,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt 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z5slpcST}!$8~P7WhC{jTkZBebrDfGX>qt%S4M-;Nv$%o<= zszHu|jpJD5?qJimvJMdQpFucx+aITouUdP_+smI6qL_!#ugDh zN}&D!wbIJZ=~NM2OaCmL(JE0eo`y7Ps(3hK2h=w5YoGVQc9Ny|U|vqAtCg!0C$0W9 z0z)4AdXeNv_SWR7kuBoE1}-HG1G6qnWAer+f!zL;&369C<|K!+^zFa4BoPtmkV3iF zQ(BqSO)6r3wSmd*%x=@4aJB2a#rzbE@&+iQ{R|4!LT0YNwbSoAM{oxJ9xPNZKtbPp z%w?(0Bx7=65BoY!Rwt0`vVXq&VZlqwuh-SpTg}?pYV-GSg-yDasXuWD0a)kuw zYiJcYPers6>b%SE`M +# Parameter : start_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# V0.2 : ama 02.2023 -- Adapted for Diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Diamond +# + +if ($verbose == 1) { + print "$separator\n\n"; + print "Launching Diamond from $designerExe\n"; + print $indent, "* Project file spec: $diamondFileSpec\n\n"; + print "$separator\n\n"; +} + +system("$designerExe $diamondFileSpec"); diff --git a/zz-solutions/04-Lissajous/Scripts/start_libero.pl b/zz-solutions/04-Lissajous/Scripts/start_libero.pl new file mode 100644 index 0000000..3e11301 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/start_libero.pl @@ -0,0 +1,37 @@ +#!/usr/bin/perl +# filename: start_libero.pl +# created by: Corthay Francois & Zahno Silvan +# +#------------------------------------------------------------------------------- +# +# Description: +# Starts Libero in the correct timezone for the Synplify License +# Help Parameter : +# Parameter : start_libero.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : zas 08.2019 -- Initial release +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; + +#------------------------------------------------------------------------------- +# Launch Libero +# + +if ($verbose == 1) { + print "\n"; + print "launching $designerExe\n"; + print $indent, "project file spec: $liberoFileSpec\n"; + print "$separator\n"; +} + +system("$designerExe $liberoFileSpec"); \ No newline at end of file diff --git a/zz-solutions/04-Lissajous/Scripts/trimLibs.pl b/zz-solutions/04-Lissajous/Scripts/trimLibs.pl new file mode 100644 index 0000000..efbff23 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/trimLibs.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ------------------------------------------------------------------------------ +# Changelog: +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/zz-solutions/04-Lissajous/Scripts/update_diamond.pl b/zz-solutions/04-Lissajous/Scripts/update_diamond.pl new file mode 100644 index 0000000..92e9076 --- /dev/null +++ b/zz-solutions/04-Lissajous/Scripts/update_diamond.pl @@ -0,0 +1,129 @@ +#!/usr/bin/perl +# filename: update_diamond.pl +# created by: Corthay Francois & Zahno Silvan & Amand Axel +# +#------------------------------------------------------------------------------- +# +# Description: +# Updates the file references in the .ldf Lattice project file +# and launches the Diamond project manager +# Help Parameter : +# Parameter : update_diamond.pl +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# V0.3 : ama 02.2023 -- Adapted for diamond +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; +$| = 1; # forces flush on prints + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{DIAMOND_HOME}\\bin\\nt64\\pnmain.exe"; +$diamondFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$lpfFileSpec = $ARGV[2]; + +use File::Basename; +$diamond_dir = dirname(dirname($vhdlFileSpec)) . '/diamond/'; # get up concat and into diamond +$projectTitle = basename($diamondFileSpec, ".ldf"); + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * diamondFileSpec: $diamondFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * lpfFileSpec: $lpfFileSpec\n"; + print " * Project title: $projectTitle\n" +} + + +#------------------------------------------------------------------------------- +# Project variables +# + +$diamondWorkFileSpec = $diamondFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{DIAMOND_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n\n"; + print "Updating file specifications in $diamondFileSpec\n"; + print $indent, "temporary file spec: $diamondWorkFileSpec\n"; +} +my $line; +if ( !open(DiamondFile, $diamondFileSpec) ){ + print("\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"); + die "\nCould not open $diamondFileSpec !\nExiting (failure)\n\n"; +} + +open(workFile, ">$diamondWorkFileSpec"); +while (chop($line = )) { + + # replace title + if ($line =~ m/ +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +# Parameter : update_libero.pl <^PDC File Spec> +#------------------------------------------------------------------------------- +# +# History: +# V0.1 : cof 12.2013 -- Initial release +# V0.2 : zas 08.2019 -- Changed actel to libero +# +################################################################################ + +$separator = '-' x 79; +$indent = ' ' x 2; +$verbose = 1; + +$ENV{TZ} = ''; # needed to be able to run Synplify avoinding license error +my $designerExe = "$ENV{LIBERO_HOME}\\Designer\\bin\\libero.exe"; +$liberoFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$pdcFileSpec = $ARGV[2]; + + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * liberoFileSpec: $liberoFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * pdcFileSpec: $pdcFileSpec\n"; +} + + + +#------------------------------------------------------------------------------- +# Project variables +# +$liberoWorkFileSpec = $liberoFileSpec . '.tmp'; + # source directory +my $sourceDir = "$ENV{CONCAT_DIR}"; +my $projectDir = "$ENV{LIBERO_WORK_DIR}"; + +#------------------------------------------------------------------------------- +# Update paths in the project file +# + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $liberoFileSpec\n"; + print $indent, "temporary file spec: $liberoWorkFileSpec\n"; +} +my $line; + +open(LiberoFile, $liberoFileSpec) || die "couldn't open $HDLFileSpec!"; +open(workFile, ">$liberoWorkFileSpec"); +while (chop($line = )) { + # replace source path + if ($line =~ m/DEFAULT_IMPORT_LOC/i) { + $line =~ s/".*"/"$sourceDir"/; + } + # replace project path + if ($line =~ m/ProjectLocation/i) { + $line =~ s/".*"/"$projectDir"/; + } + # replace VHDL file spec + if ($line =~ m/VALUE\s".*,hdl"/i) { + $line =~ s/".*"/"$vhdlFileSpec,hdl"/; + } + # replace PDC file spec + if ($line =~ m/VALUE\s".*\.pdc,pdc"/i) { + $line =~ s/".*"/"$pdcFileSpec,pdc"/; + } + + print workFile ("$line\n"); +} + +close(workFile); +close(LiberoFile); + + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($liberoFileSpec); +rename($liberoWorkFileSpec, $liberoFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#------------------------------------------------------------------------------- +# Launch Libero +# + +#if ($verbose == 1) { +# print "\n"; +# print "launching $designerExe\n"; +# print $indent, "project file spec: $liberoFileSpec\n"; +# print "$separator\n"; +#} + +#system("$designerExe $liberoFileSpec"); diff --git a/zz-solutions/04-Lissajous/Simulation/DAC.do b/zz-solutions/04-Lissajous/Simulation/DAC.do new file mode 100644 index 0000000..114f8fd --- /dev/null +++ b/zz-solutions/04-Lissajous/Simulation/DAC.do @@ -0,0 +1,31 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /dac_tb/reset +add wave -noupdate /dac_tb/clock +add wave -noupdate -divider {parallel to serial} +add wave -noupdate -format Analog-Step -height 100 -max 66000.0 -radix unsigned -subitemconfig {/dac_tb/parallelin(15) {-radix unsigned} /dac_tb/parallelin(14) {-radix unsigned} /dac_tb/parallelin(13) {-radix unsigned} /dac_tb/parallelin(12) {-radix unsigned} /dac_tb/parallelin(11) {-radix unsigned} /dac_tb/parallelin(10) {-radix unsigned} /dac_tb/parallelin(9) {-radix unsigned} /dac_tb/parallelin(8) {-radix unsigned} /dac_tb/parallelin(7) {-radix unsigned} /dac_tb/parallelin(6) {-radix unsigned} /dac_tb/parallelin(5) {-radix unsigned} /dac_tb/parallelin(4) {-radix unsigned} /dac_tb/parallelin(3) {-radix unsigned} /dac_tb/parallelin(2) {-radix unsigned} /dac_tb/parallelin(1) {-radix unsigned} /dac_tb/parallelin(0) {-radix unsigned}} /dac_tb/parallelin +add wave -noupdate -format Analog-Step -height 100 -max 32000.0 -min -32000.0 -radix decimal /dac_tb/i_dut/parallelin1 +add wave -noupdate -format Analog-Step -height 50 -max 1000000.0 -min -1000000.0 -radix decimal -subitemconfig {/dac_tb/i_dut/acc1(23) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(22) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(21) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(20) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(19) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(18) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(17) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(16) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(15) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(14) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(13) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(12) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(11) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(10) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(9) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(8) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(7) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(6) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(5) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(4) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(3) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(2) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(1) {-height 15 -radix decimal} /dac_tb/i_dut/acc1(0) {-height 15 -radix decimal}} /dac_tb/i_dut/acc1 +add wave -noupdate -format Analog-Step -height 50 -max 1000000.0 -min -1000000.0 -radix decimal -subitemconfig {/dac_tb/i_dut/acc2(23) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(22) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(21) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(20) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(19) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(18) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(17) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(16) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(15) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(14) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(13) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(12) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(11) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(10) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(9) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(8) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(7) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(6) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(5) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(4) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(3) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(2) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(1) {-height 15 -radix decimal} /dac_tb/i_dut/acc2(0) {-height 15 -radix decimal}} /dac_tb/i_dut/acc2 +add wave -noupdate /dac_tb/serialout +add wave -noupdate -divider {serial to parallel} +add wave -noupdate -format Analog-Step -height 100 -max 65500.000000000007 -radix unsigned /dac_tb/lowpassout +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 175 +configure wave -valuecolwidth 63 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {105 us} +run 100 us + diff --git a/zz-solutions/04-Lissajous/Simulation/lissajousGenerator.do b/zz-solutions/04-Lissajous/Simulation/lissajousGenerator.do new file mode 100644 index 0000000..1f4b42f --- /dev/null +++ b/zz-solutions/04-Lissajous/Simulation/lissajousGenerator.do @@ -0,0 +1,32 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /lissajousgenerator_test/reset +add wave -noupdate /lissajousgenerator_test/clock +add wave -noupdate -divider Sinewaves +add wave -noupdate -format Analog-Step -height 100 -max 65000.0 -radix unsigned -radixshowbase 0 /lissajousgenerator_test/I_DUT/sineX +add wave -noupdate -format Analog-Step -height 100 -max 65000.0 -radix unsigned -radixshowbase 0 /lissajousgenerator_test/I_DUT/sineY +add wave -noupdate -divider Sigma-delta +add wave -noupdate /lissajousgenerator_test/xSerial +add wave -noupdate /lissajousgenerator_test/ySerial +add wave -noupdate -divider {Lowpass outputs} +add wave -noupdate -format Analog-Step -height 100 -max 65000.0 -radix unsigned -childformat {{/lissajousgenerator_test/xLowapss(15) -radix unsigned} {/lissajousgenerator_test/xLowapss(14) -radix unsigned} {/lissajousgenerator_test/xLowapss(13) -radix unsigned} {/lissajousgenerator_test/xLowapss(12) -radix unsigned} {/lissajousgenerator_test/xLowapss(11) -radix unsigned} {/lissajousgenerator_test/xLowapss(10) -radix unsigned} {/lissajousgenerator_test/xLowapss(9) -radix unsigned} {/lissajousgenerator_test/xLowapss(8) -radix unsigned} {/lissajousgenerator_test/xLowapss(7) -radix unsigned} {/lissajousgenerator_test/xLowapss(6) -radix unsigned} {/lissajousgenerator_test/xLowapss(5) -radix unsigned} {/lissajousgenerator_test/xLowapss(4) -radix unsigned} {/lissajousgenerator_test/xLowapss(3) -radix unsigned} {/lissajousgenerator_test/xLowapss(2) -radix unsigned} {/lissajousgenerator_test/xLowapss(1) -radix unsigned} {/lissajousgenerator_test/xLowapss(0) -radix unsigned}} -radixshowbase 0 -subitemconfig {/lissajousgenerator_test/xLowapss(15) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(14) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(13) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(12) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(11) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(10) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(9) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(8) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(7) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(6) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(5) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(4) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(3) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(2) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(1) {-height 17 -radix unsigned -radixshowbase 0} /lissajousgenerator_test/xLowapss(0) {-height 17 -radix unsigned -radixshowbase 0}} /lissajousgenerator_test/xLowapss +add wave -noupdate -format Analog-Step -height 100 -max 65000.0 -radix unsigned -radixshowbase 0 /lissajousgenerator_test/yLowpass +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {101600 ns} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 274 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ms +update +WaveRestoreZoom {0 ns} {2100 us} +run 2 ms diff --git a/zz-solutions/04-Lissajous/Simulation/sineGen.do b/zz-solutions/04-Lissajous/Simulation/sineGen.do new file mode 100644 index 0000000..df337bb --- /dev/null +++ b/zz-solutions/04-Lissajous/Simulation/sineGen.do @@ -0,0 +1,36 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /sinegen_tb/reset +add wave -noupdate /sinegen_tb/clock +add wave -noupdate -format Analog-Step -height 30 -max 1300.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/phase +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/triangle +add wave -noupdate -divider sinewave +add wave -noupdate -format Analog-Step -height 80 -max 43200.0 -min -32800.0 -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/sineSamples +add wave -noupdate /sinegen_tb/I_DUT/newPolynom +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/a +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/b +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/c +add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/d +add wave -noupdate -format Analog-Step -height 80 -max 76000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 250 +configure wave -valuecolwidth 52 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {52589 ns} +run 50 us diff --git a/zz-solutions/04-Lissajous/Simulation/waveformGen.do b/zz-solutions/04-Lissajous/Simulation/waveformGen.do new file mode 100644 index 0000000..ce4b33d --- /dev/null +++ b/zz-solutions/04-Lissajous/Simulation/waveformGen.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /waveformgen_tb/reset +add wave -noupdate /waveformgen_tb/clock +add wave -noupdate /waveformgen_tb/en +add wave -noupdate -divider {generator signals} +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sawtooth +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/square +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/triangle +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/polygon +add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sine +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ns} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 272 +configure wave -valuecolwidth 89 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ns} {525 us} +run 500 us diff --git a/zz-solutions/04-Lissajous/lissajous.bash b/zz-solutions/04-Lissajous/lissajous.bash new file mode 100644 index 0000000..933ab09 --- /dev/null +++ b/zz-solutions/04-Lissajous/lissajous.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/zz-solutions/04-Lissajous/lissajous.bat b/zz-solutions/04-Lissajous/lissajous.bat new file mode 100644 index 0000000..983c9d9 --- /dev/null +++ b/zz-solutions/04-Lissajous/lissajous.bat @@ -0,0 +1,81 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=0 +set REQUIRE_DIAMOND=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof