From cf05b0a7f949235edd1a1f6b2779b7c30a9588ad Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 8 Mar 2024 16:16:59 +0100 Subject: [PATCH] add trigger + shift register + coeff --- 02-SplineInterpolator/Prefs/hds.hdp | 3 +- ...nterpolatorCoefficients_studentVersion.vhd | 28 +++++++++++++++--- ...terpolatorShiftRegister_studentVersion.vhd | 27 ++++++++++++++--- .../interpolatorTrigger_studentVersion.vhd | 25 +++++++++++++++- .../hdl/sineTable_studentVersion.vhd | 11 ++++--- .../SplineInterpolator/hds/.cache.dat | Bin 6746 -> 6746 bytes .../hds/sine@gen/struct.bd.lck | 6 ++++ .../SplineInterpolator_test/hds/.cache.dat | Bin 1571 -> 1571 bytes 8 files changed, 85 insertions(+), 15 deletions(-) create mode 100644 02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd.lck diff --git a/02-SplineInterpolator/Prefs/hds.hdp b/02-SplineInterpolator/Prefs/hds.hdp index 3a75d9b..2338cc0 100644 --- a/02-SplineInterpolator/Prefs/hds.hdp +++ b/02-SplineInterpolator/Prefs/hds.hdp @@ -1,11 +1,10 @@ -[Concat] [ModelSim] SplineInterpolator = $SCRATCH_DIR/SplineInterpolator SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test WaveformGenerator = $SCRATCH_DIR/WaveformGenerator WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test [hdl] -ieee = $HDS_HOME/hdl_libs/ieee/hdl +ieee = $HDS_HOME\hdl_libs\ieee\hdl SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hdl SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hdl std = $HDS_HOME/hdl_libs/std/hdl diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd index f213fce..c3f3086 100644 --- a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd @@ -1,7 +1,27 @@ ARCHITECTURE studentVersion OF interpolatorCoefficients IS + +subtype sample is signed(bitNb-1 DOWNTO 0); +subtype coeff is signed(coeffBitNb-1 DOWNTO 0); + +type samples_type is array (1 to 4) of coeff; +signal samples: samples_type; + BEGIN - a <= (others => '0'); - b <= (others => '0'); - c <= (others => '0'); - d <= (others => '0'); +-- a = - sample1 +3·sample2 -3·sample3 + sample4 +-- b = 2·sample1 -5·sample2 +4·sample3 - sample4 +-- c = - sample1 + sample3 +-- d = sample2 + + process(sample1, sample2, sample3, sample4) begin + samples(4) <= resize(sample1, coeff'high+1); + samples(3) <= resize(sample2, coeff'high+1); + samples(2) <= resize(sample3, coeff'high+1); + samples(1) <= resize(sample4, coeff'high+1); + end process; + + + a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1); + b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4); + c <= samples(3) - samples(1); + d <= samples(4); END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd index 428b0ab..3b1a6c5 100644 --- a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd @@ -1,7 +1,26 @@ ARCHITECTURE studentVersion OF interpolatorShiftRegister IS + +subtype sample_type is signed(sampleIn'range); +type samples_type is array (1 to 4) of sample_type; +signal samples: samples_type; + BEGIN - sample1 <= (others => '0'); - sample2 <= (others => '0'); - sample3 <= (others => '0'); - sample4 <= (others => '0'); + + process(clock, reset) begin + if reset = '1' then + samples <= (others => (others => '0')); + elsif rising_edge(clock) then + if shiftSamples then + for i in samples_type'low to samples_type'high-1 loop + samples(i+1) <= samples(i); + end loop; + samples(1) <= sampleIn; + end if; + end if; + end process; + + sample1 <= samples(1); + sample2 <= samples(2); + sample3 <= samples(3); + sample4 <= samples(4); END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd index 9dd7350..2f77eb8 100644 --- a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd @@ -1,4 +1,27 @@ ARCHITECTURE studentVersion OF interpolatorTrigger IS + + signal counter : unsigned(counterBitNb-1 downto 0); + BEGIN - triggerOut <= '0'; + + process(clock, reset) + begin + if reset = '1' then + counter <= (others => '1'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter - 1; + end if; + end if; + end process; + + process(counter) + begin + if counter = 0 then + triggerOut <= '1'; + else + triggerOut <= '0'; + end if; + end process; + END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd index f0ce6a4..9cf4720 100644 --- a/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd +++ b/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd @@ -8,7 +8,7 @@ BEGIN phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); - sequenceTable: process(phase) + sequenceTable: process(phaseTableAddress) begin if phase(phase'high-1) = '1' then phaseTableAddress2 <= 8 - phaseTableAddress; @@ -30,9 +30,14 @@ BEGIN when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); when others => quarterSine <= (others => '-'); end case; + if phaseTableAddress2 = 0 then + if phase(phase'high-1) = '1' then + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + end if; end process quarterTable; - invert: process(quarterSine) + invert: process(quarterSine, phase(phase'high)) begin if phase(phase'high) = '1' then sine <= NOT quarterSine; @@ -40,7 +45,5 @@ BEGIN sine <= quarterSine; end if; end process invert; - - --sine <= quarterSine; END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.cache.dat b/02-SplineInterpolator/SplineInterpolator/hds/.cache.dat index 447771e777e2e7992e13bcbecb7c2dfa7a1ba582..d2da9cc3ea6b5ed86a5541037223110a40f393ae 100644 GIT binary patch delta 89 zcmca*a?51H6K3|;+9nJP%;zS*V{)Ht#Ilk7wbDNZ2Bu?R{sBhb$#$$W*kAK}28t&zp5z9s>{}GsffRT5y9qSCJSQ$ucvkKdB7UpMP cTPMHcddU9lYa;^#n;lqjgE-4(MIK8&0FoCYkpKVy diff --git a/02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd.lck b/02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd.lck new file mode 100644 index 0000000..440dbc4 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd.lck @@ -0,0 +1,6 @@ +EDIT_LOCK +remi.heredero +UNKNOWN +WE2330808 +17492 +08.03.2024-12:51:15.116000 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat b/02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat index 3e96b59a3eb8c9f87a3b2b496090024b11921457..8507b756719aed2180446abea31c28f9402a7429 100644 GIT binary patch delta 24 gcmZ3?vzTXtF%$c1Z3_klUbD$-nS3_4G0kNL09(liMF0Q* delta 24 gcmZ3?vzTXtF%$c